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ICs for Consumer Electronics
8-Bit Microcontroller, ROMLESS SDA 30C263 / SDA 30C264
Data Sheet 1996-06-01
SDA 30C263 / SDA 30C264 Revision History: Current Version: 1996-06-01 Previous Version: Page Page (in previous (in new Version) Version) Subjects (major changes since last revision)
Edition 1996-06-01 This edition was realized using the software system FrameMaker(R). Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstrae 73, 81541 Munchen (c) Siemens AG 1996. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you - get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems2 with the express written approval of the Semiconductor Group of Siemens AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
SDA 30C263 / SDA 30C264
Table of Contents 1 1.1 1.2 1.3 1.3.1 1.3.2 1.4 2 2.1 2.1.1 2.1.2 2.1.3 2.2 2.2.1 2.2.2 2.2.3 2.3 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.6 2.4 2.5 2.6 2.7 2.8 2.8.1 2.8.2 2.8.3 2.8.4 2.8.5 2.9 2.10 2.10.1 2.11 2.11.1 2.11.2 2.12 2.13 2.13.1
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Pin Definitions and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 P-MQFP-64-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 P-MQFP-80-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 CPU Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 External Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Internal Data RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Special Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Interrupt System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Interrupt Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 Interrupt Task Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Response Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Processor Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Ports and I/O-Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 General Purpose Timers/Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Multiprocessor Communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 More about Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 More about Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 More about Modes 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Pulse Width Modulation Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Analog Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Analog Detector (SDA 30C264 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 I2C Serial Interface (SDA 30C264 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Registers and Hardware-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 Operation Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91 Advanced Function Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Notes on Data Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
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Table of Contents 2.13.2 2.13.3 2.13.4 2.14 3 3.1 3.2 3.3 4 5 6
Page
Notes on Program Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Instruction Set Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Instruction Opcodes in Hexadecimal Order . . . . . . . . . . . . . . . . . . . . . . . . .100 Differences between SDA 30C263 / SDA 30C264, SDA 30C163 / SDA 30C164 and SDA 5250 . . . . . . . . . . . . . . . . . . . . . . . .107 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
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1
Introduction
The SDA 30C26x family, a derivative of the SAB C501, is a member of a family of single-chip computers, in which the emphasis is no longer placed on purely numeric computational performance, but on application-specific controller functions. Architecture and instruction set are based upon that of the 8051 microcomputer. Like the 8051 it has many features which increase programming ease; extended internal data memory-space, variable manipulation in internal data memory, free stack location in data RAM, 4 register banks, special function registers, memory mapped I/O, individually addressable bits and a Boolean processor give the programmer the ability to improve the power of software development. Numerical problems can be processed with binary as well as with BCD-arithmetic. The many bit handling instructions also contribute to the computer's efficiency as a controller. Extended memory is controlled by an 8-bit dataand a (16 + 3)-bit address bus without any additional devices such as latches or logic elements, even when all 512 K of the program address space is used. All this leads, in suitable applications, to a reduction in the peripheral hardware and to a simplification of the software and thus to reduced development and component costs. The controller, specially developed for entertainment electronic applications, can also be recommended where both lowest component costs and a large production volume are prime requirements. The SDA 30C26x family members contain a 1024 + 256-byte or a 2048 + 256-byte data memory (XRAM + RAM), two independent 16-bit timers/-counters and a seven-source, four-priority-level, nested interrupt structure, on-chip oscillator and clock circuits. The 30 digital I/O-lines include four 8-bit ports (P1 and P3 contain I/O-lines with multifunction options) and one 2-bit port. One or two serial interfaces are included, one behaves like the 8051 UART, the other is a I2C Bus interface (SDA 30C264 only). The second multifunction port consists of port P1, which alternatively can be used as up to eight independent pulse width modulated output channels (PWM). Controlled via special function registers, the PWM-circuitry provides flexibility in time resolution and system configuration. Specially the realization of D/A-outputs using pulse width modulation will be a cost saving advantage in analog applications. The internal ADC is an 8-bit, four channel converter. The input channels are P20 to P23, the analog supply are pins VDDA and VSSA. A flexible overvoltage/undervoltage detector is included (SDA 30C264 only). Port 4 can be used as a standard port or as memory extension address bits. Increased system reliability can be achieved by activating the integrated watchdog timer. Efficient use of program memory results from an instruction set consisting of 49 single-byte, 46 two-byte and 16 three-byte instructions. Using an internal clock frequency of 12 MHz, 64 instructions execute in 0.5 s and 45 instructions execute in 1.0 s. The remaining instructions (multiple and divide) require only 2 s. The number
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of bytes in each instruction and the number of oscillator periods required for execution are listed in the Instruction Set in chapter 2.13.3. Based on the SDA 30C163 and similar to the SDA 30C164, the SDA 30C26x comprise double stack size for the extension memory (32 byte) and seven additional data pointer registers. The SDA 30C263 is a reduced version of the SDA 30C264 (see feature list). The SDA 30C264 is functionally compatible to the SDA 30C164, but uses a different package and a different Reset input stage (P-MQFP-80-1 instead of P-LCC-84). If using the P-MQFP-64-1 Package, some I/O-features are not available (see chapter 1.3).
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8-Bit Microcontroller ROMLESS
SDA 30C263 / SDA 30C264
Preliminary Data 1.1 Features
CMOS IC
* SAB 8051 Architecture - On-chip oscillator and clock circuits - Binary or decimal arithmetic - Signed-overflow detection and parity computation - Integrated Boolean processor for control applications - Full depth stack for subroutine return linkage and data storage - Four priority level, nested interrupt structure - 0.5 s instruction cycle at 12 MHz internal clock rate - 8 data pointer registers * Serial Interface - Full duplex UART-interface - I2C compatible interface (SDA 30C264 only) * On-Chip RAM - Direct byte and bit addressability - Four register banks - 256 bytes of data memory, including 128 user-defined software flags - 2048 bytes of data memory accessible with MOVX-instructions (SDA 30C263: 1024 bytes) * External Program Memory Interface - 512 Kbytes of program memory may be addressed by a 8-bit data bus and a 16 + 3-bit address bus - Extension stack depth 32 byte Type SDA 30C263M SDA 30C264M SDA 30C263M2 SDA 30C264M2
Semiconductor Group
P-MQFP-64-1
P-MQFP-80-1
Ordering Code On request On request On request On request
7
Package P-MQFP-80-1 P-MQFP-80-1 P-MQFP-64-1 P-MQFP-64-1
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SDA 30C263 / SDA 30C264
* 30 Bidirectional I/O-Lines - Two 8-bit ports, one comprising up to eight programmable D/A-outputs - One 4-bit input port, also used for analog input - One 8-bit port with open drain output - One 2-bit port with optional memory extension function * Pulse Width Modulation Unit - Up to eight programmable PWM-output channels for low cost digital-to-analog conversion * Timers - Two 16-bit general purpose timers/event counters - Watchdog timer * Analog-to-Digital Converter - Four multiplexed input channels with 8-bit resolution - Overvoltage/Undervoltage Detector with interrupt capability (SDA 30C264 only)
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1.2
Pin Configuration
(top view)
P-MQFP-64-1
A18/P4.1
A17/P4.0 VDD
P0.4
P0.3
P0.2
P0.1
P0.0
VSS
D3
D2
D4
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 P0.5 P0.6 P0.7 P2.3 P2.2 P2.1 P2.0 VSSA A3 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 D5 D0 D6 D7 A10 A4 A11 A5 A9 A6 A8 A7 A13 A12 A14 A15
SDA 30C263 SDA 30C264
D1
25 24 23 22 21 20 19 18 17
A2
A1
VDDA
P3.7 P3.6 P3.5 P3.4 P3.3 P3.2
A0
P1.2
XTAL2
P1.5
ALE
P1.6
P1.7
P3.1
P1.4
P1.3
P1.1
P1.0 VSS
XTAL1
RST
A16
VDD
UEP08576
Figure 1
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P-MQFP-80-1
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 P0.5 P0.6 P0.7 P2.3 P2.2 P2.1 P2.0 VSSA N.C. N.C. N.C. VDDA N.C. N.C. P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 D5 D0 D6 A0 D7 A1 A2 A10 A3 A4 A11 A5 A9 A6 A8 A7 A13 A12 A14 A15
N.C. P3.1 P3.0 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 VSS VDD XTAL2 XTAL1 RST ALE A17/P4.0 A16 A18/P4.1
P0.4 P0.3 P0.2 P0.1 P0.0 N.C. N.C. N.C. N.C. VDD VSS N.C. N.C. N.C. N.C. N.C. D3 D2 D4 D1
SDA 30C263 SDA 30C264
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
UEP08575
Figure 2
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1.3 1.3.1
Pin Definitions and Functions P-MQFP-64-1 Function
Pin No. Symbol Input (I) Output (O) Supply (S) 44 45 46 47 48 49 50 51 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 I/O I/O I/O I/O I/O I/O I/O I/O
Port 0 is an 8-bit open drain bidirectional I/O-port. Port 0 pins that have 1 s written to them float; in this state they can be used as high-impedance inputs. The secondary functions are assigned to the pins of port 0 as follows: - - - - SCL0 (P0.0): I2C Bus Clock 0 (SDA 30C264 only) SDA0 (P0.1): I2C Bus Data 0 (SDA 30C264 only) SDA1 (P0.2): I2C Bus Data 1 (SDA 30C264 only) SCL1 (P0.3): I2C Bus Clock 1 (SDA 30C264 only)
9 8 7 6 5 4 3 not avail. 55 54 53 52
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3
I/O I/O I/O I/O I/O I/O I/O I/O I I I I
Port 1 is an 8-bit bidirectional I/O-port with internal pullup resistors. Port 1 pins that have 1 s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. These eight bits also contain the output channels of the pulse width modulation unit. The secondary functions are assigned to the pins of port 1 as follows: PWMi (P1.i): output of PWM channel i (i = 0, ..., 7). Port 2 is a multifunction port with P2.0 ... P2.3 working as digital or analog inputs.
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1.3.1
P-MQFP-64-1 (cont'd) Function
Pin No. Symbol Input (I) Output (O) Supply (S) 2 1 64 63 62 61 60 59 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 I/O I/O I/O I/O I/O I/O I/O I/O
Port 3 is an 8-bit bidirectional I/O-port with internal pullup resistors. Port 3 pins that have 1 s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. The secondary functions are assigned to the pins of port 3, as follows: - INT0 (P3.2): interrupt 0 input/timer 0 gate control input - INT1 (P3.3): interrupt 1 input/timer 1 gate control input - T0 (P3.4): counter 0 input - T1 (P3.5): counter 1 input - RxD (P3.6): serial port receive line - TxD (P3.7): serial port transmit line Alternative outputs for port 4 or address bits A17/A18 for memory extension (no input function for P-MQFP-64). Output of the inverting oscillator amplifier. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left open. Input to the inverting oscillator amplifier. A low level on this pin resets the processor. Power supply voltage Ground (0 V) Analog reference voltage Analog ground Address Latch Enable (used for test purposes)
42 43 12
P4.0 P4.1 XTAL2
O O O
13 14 11, 41 10, 40 58 56 15
XTAL1 RST
VDD VSS VDDA VSSA
I I S S S S
ALE
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1.3.1
P-MQFP-64-1 (cont'd) Function
Pin No. Symbol Input (I) Output (O) Supply (S) 37 38 39 57 27 25 23 21 22 24 28 26 19 20 18 17 16 31 33 35 36 34 32 30 29 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7
Address bus for external memory
Data bus for external memory
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1.3.2
P-MQFP-80-1
Pin No. Symbol Input (I) Function Output (O) Supply (S) 56 57 58 59 60 61 62 63 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 I/O I/O I/O I/O I/O I/O I/O I/O Port 0 is an 8-bit open drain bidirectional I/O-port. Port 0 pins that have 1 s written to them float; in this state they can be used as high-impedance inputs. The secondary functions are assigned to the pins of port 0 as follows: - - - - SCL0 (P0.0): I2C Bus Clock 0 (SDA 30C264 only) SDA0 (P0.1): I2C Bus Data 0 (SDA 30C264 only) SDA1 (P0.2): I2C Bus Data 1 (SDA 30C264 only) SCL1 (P0.3): I2C Bus Clock 1 (SDA 30C264 only)
11 10 9 8 7 6 5 4 67 66 65 64
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2.0 P2.1 P2.2 P2.3
I/O I/O I/O I/O I/O I/O I/O I/O I I I I
Port 1 is an 8-bit bidirectional I/O-port with internal pullup resistors. Port 1 pins that have 1 s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. These eight bits also contain the output channels of the pulse width modulation unit. The secondary functions are assigned to the pins of port 1 as follows: PWMi (P1.i): output of PWM-channel i (i = 0, ..., 7). Port 2 is a multifunction port with P2.0 ... P2.3 working as digital or analog inputs.
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1.3.2
P-MQFP-80-1 (cont'd)
Pin No. Symbol Input (I) Function Output (O) Supply (S) 3 2 80 79 78 77 76 75 P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 I/O I/O I/O I/O I/O I/O I/O I/O Port 3 is an 8-bit bidirectional I/O-port with internal pullup resistors. Port 3 pins that have 1 s written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. The secondary functions are assigned to the pins of port 3, as follows: - INT0 (P3.2): interrupt 0 input/timer 0 gate control input - INT1 (P3.3): interrupt 1 input/timer 1 gate control input - T0 (P3.4): counter 0 input - T1 (P3.5): counter 1 input - RxD (P3.6): serial port receive line - TxD (P3.7): serial port transmit line not connected
1, 45, 46, 47, 48, 49, 52, 53, 54, 55, 69, 70, 71, 73, 74 18 20 14
NC
NC
P4.0 P4.1 XTAL2
I/O I/O O
Alternative outputs for port 4 quasi-bidirectional I/O or address bits A17/A18 for memory extension. Output of the inverting oscillator amplifier. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left open. Input to the inverting oscillator amplifier. A low level on this pin resets the processor. Power supply voltage Ground (0 V) Analog reference voltage Analog ground
15 16 13, 51 12, 50 72 68
XTAL1 RST
I I S S S S
VDD VSS VDDA VSSA
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1.3.2
P-MQFP-80-1 (cont'd)
Pin No. Symbol Input (I) Function Output (O) Supply (S) 17 37 35 34 32 31 29 27 25 26 28 33 30 23 24 22 21 19 39 41 43 44 42 40 38 36 ALE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7 Address Latch Enable (used for test purposes) Address bus for external memory
Data bus for external memory
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1.4
Functional Block Diagram
XTAL1
XTAL 2
OSC & Timing
RAM 2048 x 8
1)
RAM 256 x 8
Bus Interface Memory Ext.
A0 ... A15 D0 ... D7 ALE
RST
CPU
Port 0
Port 0 8-Bit Port 1 8-Bit Port 2 4-Bit ADC Input Port 3 8-Bit Port 4 2-Bit
Port 1 Timer 0 Port 2 Timer 1 Port 3 ADC Port 4 8 Channel PWM Unit Watchdog Timer UART Serial Interface
2)
C
2
1) 2)
SDA 30C263 : 1024 x 8 only SDA 30C264 only
UEB08577
Figure 3
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2 2.1
Functional Description Architecture
The CPU manipulates operands in three memory spaces. These are the program memory (512 Kbyte) and (256 + 1024/2048) byte internal data memory spaces. The program memory address space is provided to accommodate relocatable code. The internal data memory address space is further divided into the 256-byte internal data RAM, 1024/2048 bytes XRAM and the 128-byte Special Function Register (SFR) address spaces. Four register banks (each bank has eight registers),128 addressable bits, and the stack reside in the internal data RAM. The stack depth is limited only by the available internal data RAM. It's location is determined by the 8-bit stack pointer. All registers except the program counter and the four 8-register banks reside in the special function register address space. These memory mapped registers include arithmetic registers, pointers, I/O-ports, registers for the interrupt system, timers, pulse width modulator and serial channel. Many locations in the SFR address space are addressable as bits. Note that reading from unused locations in internal data memory will yield undefined data. Conditional branches are performed relative to the program counter. The register-indirect jump permits branching relative to a 16-bit base register with an offset provided by an 8-bit index register. Sixteen-bit jumps and calls permit branching to any location within one 64 K block of the 512 K program memory address space. There are five methods for addressing source operands: register, direct, register-indirect, immediate, and base-register plus index-register indirect addressing. The first three methods can be used for addressing destination operands. Most instructions have a `destination, source' field that specifies the data type, addressing methods and operands involved. For operations other than moves, the destination operand is also a source operand. Registers in the four 8-register banks can be accessed through register, direct, or register-indirect addressing; the lower 128 bytes of internal data RAM through direct or register-indirect addressing, the upper 128 bytes of internal data RAM through register-indirect addressing; and the special function registers through direct addressing. Look-up tables resident in program memory can be accessed through base-register plus index-register indirect addressing.
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2.1.1
CPU Hardware
Instruction Decoder Each program instruction is decoded by the instruction decoder. This unit generates the internal signals that control the functions of each unit within the CPU section. These signals control the sources and destination of data, as well as the function of the Arithmetic/Logic Unit (ALU). Program Control Section The program control section controls the sequence in which the instructions stored in program memory are executed. The conditional branch logic enables conditions internal and external to the processor to cause a change in the sequence of program execution. The 16-bit program counter holds the address of the instruction to be executed. It is manipulated with the control transfer instructions listed in chapter `Instruction Set'. Internal Data RAM The internal data RAM provides a 256-byte scratch pad memory, which includes four register banks and 128 direct addressable software flags. Each register bank contains registers R0 ... R7. The addressable flags are located in the 16-byte locations starting at byte address 32 and ending with byte location 47 of the RAM-address space. In addition to this standard internal data RAM the processor contains additional 1024/2048 bytes internal RAM. It can be considered as a part of an external data memory. It is located at addresses 63488 to 65535 of the external data memory address space and is referenced by MOVX instructions (MOVX A, @DPTR). Arithmetic/Logic Unit (ALU) The arithmetic section of the processor performs many data manipulation functions and includes the Arithmetic/Logic Unit (ALU) and the A, B and PSW registers. The ALU accepts 8-bit data words from one or two sources and generates an 8-bit result under the control of the instruction decoder. The ALU performs the arithmetic operations of add, subtract, multiply, divide, increment, decrement, BCD-decimal-add-adjust and compare, and the logic operations of and, or, exclusive-or, complement and rotate (right, left, or nibble swap). The A-register is the accumulator, the B-register is dedicated during multiply and divide and serves as both a source and a destination. During all other operations the B-register is simply another location of the special function register space and may be used for any purpose.
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Boolean Processor The Boolean processor is an integral part of the processor architecture. It is an independent bit processor with its own instruction set, its own accumulator (the carry flag) and its own bit- addressable RAM and l/O. The bit manipulation instructions allow the direct addressing of 128 bits within the internal data RAM and several bits within the special function registers. The special function registers which have addresses exactly divisible by eight contain directly addressable bits. The Boolean processor can perform, on any addressable bit, the bit operations of set, clear, complement, jump-if-set, jump-if-not-set, jump-if-set then-clear and move to/from carry. Between any addressable bit (or its complement) and the carry flag it can perform the bit operation of logical AND or logical OR with the result returned to the carry flag. Program Status Word Register (PSW) The PSW flags record processor status information and control the operation of the processor. The carry (CY), auxiliary carry (AC), two user flags (F0 and F1), register bank select (RS0 and RS1), overflow (OV) and parity (P) flags reside in the program status word register. These flags are bit-memory-mapped within the byte-memory-mapped PSW. The CY, AC, and OV flags generally reflect the status of the latest arithmetic operations. The CY-flag is also the Boolean accumulator for bit operations. The P-flag always reflects the parity of the A-register. F0 and F1 are general purpose flags which are pushed onto the stack as part of a PSW-save. The two register bank select bits (RS1 and RS0) determine which one of the four register banks is selected as follows: RS1 0 0 1 1 RS0 0 1 0 1 Register Bank 0 1 2 3 Register Location 00H ... 07H 08H ... 0FH 10H ... 17H 18H ... 1FH
Program Status Word Default after reset: 00H (MSB) CY AC F0
PSW
SFR Address D0H
(LSB) RS1 RS0 OV F1 P
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Stack Pointer (SP) The 8-bit stack pointer contains the address at which the last byte was pushed onto the stack. This is also the address of the next byte that will be popped. The SP is incremented during a push. SP can be read or written to under software control. The stack may be located anywhere within the internal data RAM address space and may be as large as 256 bytes. Data Pointer Register (DPTR) The 16-bit Data Pointer Register DPTR is the concatenation of registers DPH (high-order byte) and DPL (low-order byte). The DPTR is used in register-indirect addressing to move program memory constants and to access the extended data memory. DPTR may be manipulated as one 16-bit register or as two independent 8-bit registers DPL and DPH. Eight data pointer registers are available, the active one is selected by a special function register (DPSEL). 2.1.2 CPU Timing
Timing generation is completely self-contained, except for the frequency reference which can be a crystal or external clock source. The on-board oscillator is a parallel anti-resonant circuit with a frequency range of 1 MHz to 12 MHz. There is a divide-by-6 internal timing which leads to a minimum instruction cycle of 0.5 s with a 12-MHz crystal. The XTAL2-pin is the output of a high-gain amplifier, while XTAL1 is its input. A crystal connected between XTAL1 and XTAL2 provides the feedback and phase shift required for oscillation. The 1 MHz to 12 MHz range is also accommodated when an external clock is applied to XTAL1 as the frequency source. In this specification all timings are referenced to an internal clock. The relationship between the internal clock and the oscillator frequency depends on the setting of CDC in special function register AFR. If CDC is set to `1' (which is the reset value) the internal clock is half the external oscillator frequency, if CDC is reset to `0' the internal clock is equal to the external oscillator frequency. A machine cycle consists of 6 internal clocks. Most instructions execute in one cycle. MUL (multiply) and DIV (divide) are the only instructions that take more than two cycles to complete. They take four cycles. Normally, two code bytes are fetched from program memory during every machine cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a 1-byte 2-cycle instruction that accesses XRAM. During a MOVX, two fetches are skipped while the internal XRAM is being addressed.
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2.1.3
Addressing Modes
There are five general addressing modes operating on bytes. One of these five addressing modes, however, operates on both bytes and bits: - - - - - register direct (both bytes and bits) register indirect immediate base-register plus index-register indirect
The following table summarizes, which memory spaces may be accessed by each of the addressing modes: Register Addressing R0 ... R7 ACC, B, CY (bit), DPTR Direct Addressing RAM (low part) Special Function Registers Register-Indirect Addressing RAM (@R1, @R0, SP) Immediate Addressing Program Memory Base-Register plus Index-Register Indirect Addressing Program Memory (@DPTR + A, @PC + A) Register Addressing Register addressing accesses the eight working registers (R0 ... R7) of the selected register bank. The PSW register flags RS1 and RS0 determine which register bank is enabled. The least significant three bits of the instruction opcode indicate which register is to be used. ACC, B, DPTR and CY, the Boolean processor accumulator, can also be addressed as registers.
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Direct Addressing Direct byte addressing specifies an on-chip RAM-location (only low part) or a special function register. Direct addressing is the only method of accessing the special function registers. An additional byte is appended to the instruction opcode to provide the memory location address. The highest-order bit of this byte selects one of two groups of addresses: values between 0 and 127 (00H ... 7FH) access internal RAM locations, while values between 128 and 255 (80H ... 0FFH) access one of the special function registers. Register-Indirect Addressing Register-indirect addressing uses the contents of either R0 or R1 (in the selected register bank) as a pointer to locations in the 256 bytes of internal RAM. Note that the special function registers are not accessable by this method. Execution of PUSH- and POP-instructions also use register-indirect addressing. The stack pointer may reside anywhere in internal RAM. Immediate Addressing Immediate addressing allows constants to be part of the opcode instruction in program memory. An additional byte is appended to the instruction to hold the source variable. In the assembly language and instruction set, a number sign (#) precedes the value to be used, which may refer to a constant, an expression, or a symbolic name. Base-Register plus Index Register-Indirect Addressing Base-register plus index register-indirect addressing allows a byte to be accessed from program memory via an indirect move from the location whose address is the sum of a base register (DPTR or PC) and index register, ACC. This mode facilitates accessing to look-up-table resident in program memory.
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2.2
Memory Organization
The processor memory is organized into four address spaces. The memory spaces are: - 512-Kbyte external program memory address space - 256 byte plus 128-byte internal data memory address space - 1024/2048-byte additional internal data memory A 16-bit program counter and a dedicated banking logic provide the processor with its 512-Kbyte addressing capabilities (up to 19 address lines are available). The program counter allows the user to execute calls and branches to any location within the program memory space. There are no instructions that permit program execution to move from the program memory space to the data memory space. 2.2.1 External Program Memory
Certain locations in program memory are reserved for specific programs. Locations 0000H through 0002H are reserved for the initialization program. Following reset, the CPU always begins execution at location 0000H. Locations 0003H through 0033H are reserved for the interrupt service routines. Memory Extension The processor is prepared to extend its external program memory space up to 512 Kbytes (figure 4, 5). For easy handling of existing software and assemblers this space is split into 8 banks of 64 Kbytes each. The extension concept, based on the standard 64 K addressing ability, is provided for high effective and easy memory access with minimum software overhead. There is also no need caring about bank organization during subroutine processing or interrupts. This is done through address bits A16 ... 18, which are controlled by a special internal circuitry, performing a `delayed banking'. The operations to the extended memory spaces are controlled by two additional special function registers called MEX1 and MEX2 (figure 4). The address bits A17 and A18 are implemented at Port 4. Programs, using only 128-Kbytes program memory space, may switch the address function off by setting bits NB, IB and bits MB to `1' followed by a LJMP. Then port 4 will work properly in port mode. Whenever full address mode is desired, port 4 bits have to be kept on `1' (table 1). After reset all CB are `0' and P4 latches are set to `1', resulting a `0' at the port 4 pins.
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Banking of Program Memory After reset the bits for current bank (CB) and next bank (NB) are set to zero. This way the processor starts the same as any 8051 controller at address 00000H. Whenever a jump to another bank is required, the software has to change the bits NB16 ... 18 for initializing the bank exchange (bits CB16 ... 18 are read only). After operating the next LJMP instruction the NB16 ... 18 bits (next bank) are copied to CB16 ... 18 (current bank) and will appear at A16 ... 18. If enabled by DJMP in SFR AFR, JMP@A + DPTR will perform the same operation.
P0 P1 P2 P3 P4 D D EPROM A A OE
UES08578
SDA 30C263 30C264
Figure 4 Connecting External Program Memory
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524287 458751 393215 327679 262143 196607 131071 65535 2 1 Bank 0 0000 3 4 5 6 7 458752 393216 327680 262144 196608 131072 65536
UEC04716
Figure 5 Bank Organization
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Figure 6 Register Bits MEX1 and MEX2 Memory Extension Bank Default after reset: X000 X000B (MSB) - CB18 CB17 CB16 MEX2 - NB18 NB17 (LSB) NB 16 SFR Address 95H MEX1 SFR Address 94H
Memory Extension Mode Default after reset: 00H (MSB) MM CB NB MM MB SF IB MB18 MB17
(LSB) MB16 SF IB18 IB17 IB16
= Current Bank = Next Bank = Memory Mode = Memory Bank = Stack Full = Interrupt Bank
Read only; CBx = Ax R/W R/W; `1' = use MB R/W Read only; `1' = full R/W
Table 1 Port 4 Configuration CB 0 0 1 1 MOVC Handling MOVC instructions may operate in two different modes, that are selected by bit MM in MEX2. On MM = `0' MOVC will access the current bank. On MM = `1' the bits MB16 ... 18 will appear at A16 ... A18 during MOVC. P4 Latch 0 1 0 1 P4 Out 0 0 0 1 Address P4 Addr / P4 Comment
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Bank 3 Bank 2
DPTR PC MM=1, MB16-17 =3, CB 16-17 =2
UEC04717
Figure 7 PC and DPTR on Different Banks CALLs and Interrupts For flexible use of CALL and interrupts the control logic holds an own 32 levels-six-bit-stack. Whenever a LCALL or ACALL occurs, CB16 ... 18 and NB16 ... 18 (MEX1) is copied to this stack and the memory extension stackpointer is incremented. Then NB16 ... 18 is copied to CB16 ... 18. Leaving subroutines through RET or RETI decrements the stack pointer and reads the old NB and CB contents from the stack. All six bits are required for saving to prevent conflicts on interrupt events. One additional feature simplifies the handling of interrupts: on occurrence the bits IB16 ... 18 within MEX2 are copied to CB16 ... 18 and NB16 ... 18 after pushing their old contents on the stack. This way programmers can place their ISR (Interrupt Service Routine) on specific banks. After reset MM, MB16 ... 18 and IB16 ... 18 are set to zero. In order to prevent loss of program control during deep subroutine nesting a warning bit `SF' (Stack Full) is set in MEX2 whenever a memory extension stack depth overflow is imminent. For example figure 8 shows the data flows at the memory extension stack during a LCALL. All three bits of NB are copied to the position CB and NB of the next higher stack level (now the current MEX1) while the last CB and NB are held on the stack. Returning from subroutine through RET the memory extension stack pointer decrements and CB and NB of MEX1 has the same contents as before LCALL.
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Before CB NB
'LCALL'
After CB NB
MEX1 MEX1 010 110 010 110
110 010
110 110
MEX1:
CB 18,17,16
NB 18,17,16
UEC04718
Figure 8 Processing LCALL (same as ACALL) Examples The standard sequence jumping from one bank to another is simply preceding a `MOV MEX1,#'- instruction to an `LJMP/LCALL' as shown in figure 8. To operate programs up to 512 Kbytes with standard assemblers or from C the program can be split into sections, modules or files, that will each run in their own bank. Referencing banks to each other (jumps, calls, data moves) may be done by a simple preprocessing of the source programs or object files. Users, going to program a 512-Kbyte EPROM in assembler, may proceed like this: 1. Build up to eight assembler source files (max. 64 K), inter bank operations will refer to dummy labels. 2. Do assembler runs on each block and generate label lists. 3. Preprocessing: substitute the inter bank labels in the source files with absolute 64 K addresses. 4. Second and final assembler runs on each block, generate Hex files. 5. Append the Hex files in right order. 6. Program an EPROM. More comfortable programming, e.g. based on C-programs, require similar processing of the source programs or object files with respect to special considerations of the compiler.
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Figure 9 shows an assembler program run, performing the following actions: 1. Start at bank 0 at 00000H. 2. Set ISR-page to bank 2. 3. Jump to bank 1 at address 25. 4. Being interrupted to bank 2 ISR. 5. Call a subprogram at bank 2 address 43. 6. After return read data from bank 2.
Bank 2 Bank 1 Bank 0 ORG 25 ORG 40 ;set ISR Bank = Bank 2 0040: PRGM0: MOV MEX2,#02 ;Prepare jumping ;from ;Bank 0 to Bank 1 0043: 0046: MOV MEX1,#1 LJMP 25 ;'25' is a substitution of Primary Labels transformed to an Absolute Address at Bank 2 ;Fetch Data from Bank 2 ;(and update ISR-Bank pointer) 0150: 0153: 0156: MOV MEX2,#0A2 H MOV DPTR,#100 MOVC A, @DPTR 0040: 0080: 0025: PRGM1: MOV... ;Prepare ;Calling PRGM2 ;on Bank 2 MOV MEX1,#2 LCALL 43 Interrupt RETI ORG 43 0043: 0060: PRGM2: ;Execute PRGM2 RET ORG 100 0100: BYTE 44 H 0013: ;ISR on ;Bank 2 ORG 13
to AKKU
UEC04719
Figure 9 Program Example 2.2.2 Internal Data RAM
The internal data memory is divided into four blocks: the lower 128 byte of RAM, the upper 128 byte of RAM, the 128-byte Special Function Register (SFR) area and the 2048-byte additional RAM (figure 10). Because the upper RAM-area and the SFR area share the same address locations, they are accessed through different addressing modes. The internal data RAM-address space is 0 to 255. Four banks of eight registers each occupy locations 0 through 31. Only one of these banks may be enabled at a time through a two-bit field in the PSW. In addition, 128-bit locations of the on-chip RAM are accessible through direct addressing.
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These bits reside in internal data RAM at byte locations 32 through 47, as shown in figure 11. The lower 128 bytes of internal data RAM can be accessed through direct or register-indirect addressing, the upper 128 bytes of internal data RAM through register-indirect addressing and the special function registers through direct addressing. The stack can be located anywhere in the internal data RAM-address space. The stack depth is limited only by the available internal data RAM, thanks to an 8-bit reloadable stack pointer. The stack is used for storing the program counter during subroutine calls and may also be used for passing parameters. Any byte of internal data RAM or special function registers accessible through direct addressing can be pushed/popped. An additional on-chip RAM-space called `XRAM' extends the internal RAM-capacity up to 2304 bytes. The 1024/2048 bytes of XRAM are accessed by MOVX @DPTR. XRAM is located in the upper area of the address space at 0F800H ... 0FFFFH. Page Registers Default after reset: XXH (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 PAGE 0, 1 SFR Address A4H, A5H
Bit 7 ... Bit 0: Upper 8 bits of memory address used in MOVX@Ri instructions. PAGE0 is used together with R0, PAGE1 is used together with R1. 2.2.3 Special Function Registers
The special function register address space resides between addresses 128 and 255. All registers except the program counter and the four banks of eight working registers reside here. Memory mapping the special function registers allows them to be accessed as easily as the internal RAM. As such, they can be operated on by most instructions. A complete list of the special function registers is given in table 2. In addition, many bit locations within the special function register address space can be accessed using direct addressing. These direct addressable bits are located at byte addresses divisible by eight as shown in figure 12.
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255
255
65535
FFFF H
Internal DATA RAM
Special Function Registers
Addressable Bits in SFRs
128 127
128
Addressable Bits in RAM (128 Bits)
48 47 127 32 7 31 R 7 24 R 0 R7
120 0 BANK3 BANK2 BANK1 BANK0 Internal DATA RAM
64512 64511
FC00 H FBFFH
Registers
16 R 0 R7 8 R0 R7 0 R0
Additional Internal DATA RAM (XRAM)
SDA 30C264 only
63488
F800 H
UED08579
Figure 10 Internal Data Memory Address Space
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RAM Byte 256
(MSB)
(LSB)
47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 Bank 3 24 23 Bank 2 16 15 Bank 1 8 7 Bank 0 0 7F 77 6F 67 5F 57 4F 47 3F 37 2F 27 1F 17 0F 07 7E 76 6E 66 5E 56 4E 46 3E 36 2E 26 1E 16 0E 06 7D 75 6D 65 5D 55 4D 45 3D 35 2D 25 1D 15 0D 05 7C 74 6C 64 5C 54 4C 44 3C 34 2C 24 1C 14 0C 04 7B 73 6B 63 5B 53 4B 43 3B 33 2B 23 1B 13 0B 03 7A 72 6A 62 5A 52 4A 42 3A 32 2A 22 1A 12 0A 02 79 71 69 61 59 51 49 41 39 31 29 21 19 11 09 01 78 70 68 60 58 50 48 40 38 30 28 20 18 10 08 00
FFH
2FH 2EH 2DH 2CH 2BH 2AH 29H 28H 27H 26H 25H 24H 23H 22H 21H 20H 1FH 18H 17H 10H 0FH 08H 07H 00H
Figure 11 Internal RAM-Bit Addresses
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Direct Byte Address F8H F0H E8H E0H D8H D0H C8H C0H B8H B0H A8H A0H 98H 90H 88H 80H FF F7 - E7 DF D7 - - BF B7 AF A7 9F 97 8F 87 FE F6 - E6 DE D6 - - BE B6 AE A6 9E 96 8E 86 FD F5 - E5 - D5 - - BD B5 AD A5 9D 95 8D 85
Bit Address FC F4 - E4 DC D4 - - BC B4 AC A4 9C 94 8C 84 FB F3 - E3 DB D3 - - BB B3 AB A3 9B 93 8B 83 FA F2 - E2 - D2 - - BA B2 AA A2 9A 92 8A 82 F9 F1 E9 E1 D9 D1 - - B9 B1 A9 A1 99 91 89 81 F8 F0 E8 E0 D8 D0 - - B8 B0 A8 A0 98 90 88 80
Hardware Register Symbol PWME B P4 ACC ADCON PSW - - ICCON P3 IE P2 SCON P1 TCON P0
Figure 12 Special Function Register Bit Address Space
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Table 2 Special Function Register Overview Special Function Register Description Symbolic Name Address Address Bit Address Location Location MSB ... LSB (hex.) (dec.) (hex.) Initial Value after Reset (hex./bin.)
Arithmetic Registers Accumulator B-Register Program Status Word System Control Registers Stack Pointer Data Pointer (high byte) Data Pointer (low byte) Data Pointer Select Power Control Memory Extension Bank Memory Extension Mode Page Register 0 Page Register 1 Advanced Function Register I/O-Port Registers Port 0 Port 1 Port 2 Port 3 Port 4 Interrupt Control Registers Interrupt Enable Flags Interrupt Priority Flags 0 Interrupt Priority Flags 1 Interrupt Request Control IE IP0 IP1 IRCON A8 A9 AA AB 168 169 170 171 AF ... A8 - - - 00 00 00 x5 P0 P1 P2 P3 P4 80 90 A0 B0 E8 128 144 160 176 232 87 ... 80 97 ... 90 A7 ... A0 B7 ... B0 E9 ... E8 FF FF FF FF see note SP DPH DPL DPSEL PCON MEX1 MEX2 PAGE 0 PAGE 1 AFR 81 83 82 A2 87 94 95 A4 A5 A6 129 131 130 162 135 148 149 164 165 166 - - - - - - - - - - 07 00 00 xxxx x000 00 x000 x000 00 xx xx 0000 0xx1 ACC, A B PSW E0 F0 D0 224 240 208 E7 ... E0 F7 ... F0 D7 ... D0 00 00 00
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Table 2 Special Function Register Overview (cont'd) Special Function Register Description Symbolic Name Address Address Bit Address Location Location MSB ... LSB (hex.) (dec.) (hex.) Initial Value after Reset (hex./bin.)
Timer 0/1 Registers Timer 0/1 Mode Register Timer 0/1 Control Register Timer 1 (high byte) Timer 0 (high byte) Timer 1 (low byte) Timer 0 (low byte) Watchdog Timer Registers Watchdog Control Register Watchdog Reload Register Watchdog Low Byte Watchdog High Byte Analog Digital Converter ADC-Control Register ADC-Data Register ADC-Start Register Detector Control Register Detector Select Register Detector Lower Register Detector Upper Register ADCON ADDAT DAPR DECON DESEL DELOW DEUP D8 D9 DA DC DD DE DF 216 217 218 220 221 222 223 9F ... 98 - - - - - - 00 xx xx 0000 0xxx xx xx xx WDCON WDTREL WDTL WDTH A7 86 84 85 167 134 132 133 - - - - 0xxx xxxx 00 00 80 TMOD TCON TH1 TH0 TL1 TL0 89 88 8D 8C 8B 8A 137 136 141 140 139 138 - 8F ... 88 - - - - 00 00 00 00 00 00
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Table 2 Special Function Register Overview (cont'd) Special Function Register Description Symbolic Name Address Address Bit Address Location Location MSB ... LSB (hex.) (dec.) (hex.) Initial Value after Reset (hex./bin.)
Pulse Width Modulator Registers Enable Register Counter Register (low byte) Counter Register (high byte) Compare Register 0 Compare Register 1 Compare Register 2 Compare Register 3 Compare Register 4 Compare Register 5 PWM 14 Compare Reg. 0 PWM 14 Extension Reg. 0 PWM 14 Compare Reg. 1 PWM 14 Extension Reg. 1 Serial Interface Registers Serial Control Register Serial Data Register I2C Registers I2C Control Register I2C Mode Register I2C Shifter Register I2C Address Register I2C Baud Register 0 I2C Baud Register 1 ICCON ICMOD ICSHI ICADR ICBD0 ICBD1 B8 B9 BA BB BC BD 184 185 186 187 188 189 BF ... B8 - - - - - 0000 0x00 000x 00xx xx xx 00xx xxxx 00xx xxxx SCON SBUF 98 99 144 145 9F ... 98 - 00 xx PWME PWCL PWCH PWCOMP0 PWCOMP1 PWCOMP2 PWCOMP3 PWCOMP4 PWCOMP5 PWCOMP6 PWEXT6 PWCOMP7 PWEXT7 F8 F7 F9 F1 F2 F3 F4 F5 F6 FB FA FD FC 248 247 249 241 242 243 244 245 246 251 250 253 252 FF ... F8 - - - - - - - - - - - - 00 00 c0 00 00 00 00 00 00 00 02 00 02
Note: The P4 internal latches are set to `1', the P4 external pins are reset to `0'.
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2.3
Interrupt System
External events and the real-time on-chip peripherals require CPU-service asynchronous to the execution of any particular section of code. To couple the asynchronous activities of these functions to normal program execution, a sophisticated multiple-source, four-priority level, nested interrupt system is provided. Interrupt response delay ranges from 1.5 s to 3.5 s when using a 12-MHz internal clock. 2.3.1 Interrupt Sources
The processor acknowledges interrupt requests from seven sources: two from external sources via the INT0 and INT1 pins, one from each of the two internal counters, one from the serial I/O-port, one from the I2C interface and one from the analog digital converter. Each of the seven sources can be assigned to either of four priority levels and can be independently enabled and disabled. Additionally, all enabled sources can be globally disabled or enabled. Interrupts result in a transfer of control to a new program location. Each interrupt vectors to a separate location in program memory for its service program. The program servicing the request begins at this address. The starting address (interrupt vector) of the interrupt service program for each interrupt source is shown in the following table: Interrupt Source External Request 0 Internal Timer/Counter 0 External Request 1 Internal Timer/Counter 1 Serial Interface I2C Interface Analog Digital Converter Starting Address 03 11 19 27 35 43 51 (03H) (0BH) (13H) (1BH) (23H) (2BH) (33H)
SDA 30C264 only SDA 30C264 only
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2.3.2
Interrupt Control
The information flags, which control the entire interrupt system, are stored in eight special function registers: TCON IE IP0 IP1 SCON ICCON DECON IRCON Timer/Counter Control Register Interrupt Enable Register Interrupt Priority Register 0 Interrupt Priority Register 1 Serial Control Register I2C Control Register ADC Control Register Interrupt Request Control Register 88H A8H A9H AAH 98H B8H DCH ABH
The interrupt system is shown diagrammatically in figure 13. A source requests an interrupt by setting its associated interrupt request flag in the TCON-, SCON-, ICCON- and DECON-register, as detailed in the following table: Interrupt Source External Request 0 Internal Timer/Counter 0 External Request 1 Internal Timer/Counter 1 Serial Interface I2C Interface (SDA 30C264 only) Analog Digital Converter (SDA 30C264 only) Request Flag IE0 TF0 IE1 TF1 RI/TI IIN OV/UN Bit Location TCON.1 TCON.5 TCON.3 TCON.7 SCON.0/.1 ICCON.4 DECON.7/.6
The timer 0 and timer 1 interrupts are generated by TF0 and TF1, which are set by a rollover in their respective timer/counter register, except for timer 0 in mode 3. Within the IE-register there are eight addressable flags. Seven flags enable/disable the seven interrupt sources when set/cleared. Setting/clearing the eighth flag permits a global enable/disable of all enabled interrupt requests. All the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. This means, interrupts can be generated or pending interrupt requests can be cancelled by software.
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Input Level and Interrupt Request Flag Registers:
Interrupt ENABLE Register: Source ENABLE Global ENABLE IE.7 IP1.0
Interrupt Priority Registers: Highest Priority Level IP0.0 Lowest Priority Level
INT 0
External Interrupt RQST 0
TCON.1
IE.0
IE0 TCON.5
EX 0 IE.1 IP1.1 IPO.1
INT 1
Internal Timer 0 TF0 External Interrupt RQST 1 TCON.3 ET 0 IE.2 IP1.2 IPO.2
IE1 TCON.7
EX1 IE.3 IP1.3 IPO.3
Priority Sequence
UES08580
Internal Timer 1 TF1 SCON 1/0 Internal Serial Port RI/TI
1)
ET1 IE.4 IP1.4 IPO.4
ES IE.5 IP1.5 IPO.5
ICCON.4
Internal 2C IIN
1)
EIC IE.6
EA IP1.6 IPO.6
DECON.7/.6 Internal Analog Digital Converter OV/UN SDA 30C264 only
EAD
EA
1)
Figure 13 Interrupt System * * * * * * * Seven interrupt sources Each interrupt can be individually enabled/disabled Each interrupts can be globally enabled/disabled Each interrupt can be assigned to either of four priority levels Each interrupt vectors to a separate location in program memory Interrupt nesting to four levels External interrupt requests can be programmed to be level- or transition-activated
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Figure 14 Interrupt Enable Register IE Interrupt Enable Register Default after reset: 00H (MSB) EA EA EAD EIC ES ET1 EX1 ET0 (LSB) EX0 IE SFR Address A8H
Enables or disables all interrupts. If EA = `1', no interrupt will be acknowledged. If EA = `1', each interrupt source is individually enabled or disabled by setting or clearing its enable bit. Enables or disables the analog digital converter interrupt. If EAD = `1', this interrupt will be enabled. To be set to `0' for SDA 30C263. Enables or disables the I2C interface interrupt. If EIC = `1', this interrupt will be enabled. To be set to 0 for SDA 30C263. Enables or disables the serial interface interrupt. If ES = `1', this interrupt will be enabled. Enables or disables the timer 1 overflow interrupt. If ET1 = `1', the timer 1 interrupt is enabled. Enables or disables external interrupt 1. If EX1 = `1', external interrupt 1 is enabled. Enables or disables the timer 0 overflow interrupt. If ET0 = `1', the timer 0 interrupt is enabled. Enables or disables external interrupt 0. If EX0 = `1', external interrupt 0 is enabled.
EAD EIC ES ET1 EX1 ET0 EX0
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Figure 15 Interrupt Priority Register IP0 and IP1 Interrupt Priority Register Default after reset: 00H (MSB) - IP0.6 IP0.5 IP0.4 IP1 IP0.3 IP0.2 IP0.1 (LSB) IP0.0 IP0 SFR Address A9H
Interrupt Priority Register Default after reset: 00H (MSB) - IP1.6 IP1.5 IP1.4
SFR Address AAH
(LSB) IP1.3 IP1.2 IP1.1 IP1.0
Corresponding bit-locations in both registers are used to set the interrupt priority level of an interrupt. IP1.X 0 0 1 1 IP0.X 0 1 0 1 Function Set priority level 0 (lowest) Set priority level 1 Set priority level 2 Set priority level 3 (highest)
Bit IP1.0 / IP0.0 IP1.1 / IP0.1 IP1.2 / IP0.2 IP1.3 / IP0.3 IP1.4 / IP0.4 IP1.5 / IP0.5 IP1.6 / IP0.6
Corresponding Interrupt IE0 TF0 IE1 TF1 RI / TI IIN OV/UN
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Setting/clearing a bit in the IP register establishes its associated interrupt request priority level. If a low-priority level interrupt is being serviced, a higher-priority level interrupt will interrupt it. However, an interrupt source cannot interrupt a service program of the same or higher priority level. If two requests of different priority levels are received simultaneously, the request of higher priority level will be serviced. If requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. Thus within each priority level there is a second priority structure determined by the polling sequence, as follows: Source 1. IE0 2. TF0 3. IE1 4. TF1 5. RI/TI 6. IIN 7. OV/UN Priority within Level (highest)
(lowest)
Note that the `priority within level' structure is only used to resolve simultaneous requests of the same priority level. 2.3.3 Interrupt Nesting
The process whereby a high-level interrupt request interrupts a low-level interrupt service program is called nesting. In this case the address of the next instruction in the low-priority service program is pushed onto the stack, the stack pointer is incremented by two and processor control is transferred to the program memory location of the first instruction of the high-level service program. The last instruction of the high-priority interrupt service program must be a RETI-instruction. This instruction clears the higher `priority-level-active' flip-flop. RETI also returns processor control to the next instruction of the low-level interrupt service program. Since the lower `priority-level-active' flip-flop has remained set, high priority interrupts are re-enabled while further low-priority interrupts remain disabled.
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2.3.4
External Interrupts
The external interrupt request inputs (INT0 and INT1) can be programmed for either transition- activated or level-activated operation. Control of the external interrupts is provided by the four low- order bits of TCON and the four low-order bits of IRCON as shown in figure 17. When IT0 and IT1 are set to one, interrupt requests on INT0 and INT1 are transition-activated, else they are low-level activated. IE0 and IE1 are the interrupt request flags. These flags are set when their corresponding interrupt request inputs at INT0 and INT1, respectively, are low when sampled by the processor and the transition-activated scheme is selected by IT0 and IT1. Figure 16 Function of Lower Nibble Bits in TCON Timer and Interrupt Control Register Default after reset: 00H (MSB) TF1 TR1 TF0 TR0 IE1 IT1 IE0 (LSB) IT0 TCON SFR Address 88H
TCON.4 ... TCON.7 IE1 IT1
See chapter `General Purpose Timers/Counters' Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify edge/low level triggered external interrupts. IT1 = `1' selects transition-activated external interrupts. Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 type control bit. Set/cleared by software to specify edge/low level triggered external interrupts. IT0 = `1' selects transition-activated external interrupts.
IE0 IT0
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Figure 17 Interrupt Request Control Register Default after reset: X5H (MSB) - ERI1 EFA1 ERI0 EFA0 - - - ERI1 EFA1 ERI0 (LSB) EFA0 IRCON SFR Address ABH
Enable rising edge Interrupt 1. ERI1 = `1' enables interrupt generation if a rising edge is detected at INT1. Enable falling edge Interrupt 1. EFA1 = `1' enables interrupt generation if a falling edge is detected at INT1. Enable rising edge Interrupt 0. ERI0 = `1' enables interrupt generation if a rising edge is detected at INT0. Enable falling edge Interrupt 0. EFA0 = `1' enables interrupt generation if a falling edge is detected at INT0.
Note: The reset value maintains compatibility to Intel 8051.
- Transition-Activated Interrupts (IT0 = `1', IT1 = `1') The IE0, IE1 flags are set by a transition at INT0, INT1, respectively; they are cleared during entering the corresponding interrupt service routine. For transition-activated operation, the input must remain stable for more than six oscillator periods, but needs not to be synchronous with the oscillator. In this mode, the register IRCON adds more flexibility. Two bits are available for each external interrupt to control interrupt generation on the rising and falling edge. - Level-Activated Interrupts (IT0 = 0, IT1 = 0) The IE0, IE1 flags are set whenever INT0, INT1 are respectively sampled at low level. Sampling INT0, INT1 at high level clears IE0, IE1, respectively. For level-activated operation, if the input is low during the sampling that occurs seven oscillator periods before the end of the instruction in progress, an interrupt subroutine call is made. The level-activated input needs to be low only during the sampling that occurs seven oscillator periods before the end of the instruction in progress and may remain low during the entire execution of the service program. However, the input must be deactivated before the service routine is completed to avoid invoking a second interrupt, or else another interrupt will be generated. If an interrupt is level-activated, its corresponding bits in IRCON should be set to 0 for future compatibility.
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2.3.5
Interrupt Task Function
The processor records the active priority level(s) by setting internal flip-flop(s). Each interrupt level has its own flip-flop. The flip-flop corresponding to the interrupt level being serviced is reset when the processor executes a RETI-instruction. The sequence of events for an interrupt is: - A source provokes an interrupt by setting its associated interrupt request bit to let the processor know an interrupt condition has occurred. - The CPU's internal hardware latches the internal request in the 5th, 11th, 17th and 23th oscillator period of the instruction in progress. - The interrupt request is conditioned by bits in the interrupt enable and interrupt priority register. - The processor acknowledges the interrupt by setting one of the four internal `priority-level active' flip-flops and performing a hardware subroutine call. This call pushes the PC (but not the PSW) onto the stack and, for most sources, clears the interrupt request flag. - The service program is executed. - Control is returned to the main program when the RETI-instruction is executed. The RETI instruction also clears one of the internal `priority-level active' flip-flops. The interrupt request flags IE0, IE1, TF0 and TF1 are cleared when the processor transfers control to the first instruction of the interrupt service program. The RI/TI, IIN and OV/UN request flag must be cleared as part of the respective interrupt service program.
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2.3.6
Response Time
The highest-priority interrupt request gets serviced at the end of the instruction in progress unless the request is made in the last seven oscillator periods of the instruction in progress. Under this circumstance, the next instruction will also execute before the interrupt's subroutine call is made. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The call itself takes two cycles. Thus, a minimum of three complete machine cycles elapse between activation of an external interrupt Functional Description. lf the instruction in progress is not in its final cycle, the additional wait time cannot be more than 3 cycles, since the longest instructions (MUL and DIV) are only 4 cycles long, and if the instruction in progress is RETI or an access to IE or IP0 or IP1, the additional wait time cannot be more than 5 cycles (a maximum of one more cycle to complete the instruction in progress, plus 4 cycles to complete the next instruction if the instruction is MUL or DIV). Thus, in a single-interrupt system, the response time is always more than 3 cycles and less than 8 cycles (approximately 5.25 s at 8-MHz operation). Examples of the best and worst case conditions are illustrated in the following table.
Instruction External interrupt generated immediately before (best) / after (worst) the pin is sampled (time until end of bus cycle). Current or next instruction finishes in 6-oscillator periods Next instruction is MUL or DIV Internal latency for hardware subroutine call
Time (Internal Clocks) Best Case 1+ Worst Case 1-
6
6
don't care 12 19
24 12 43
If an interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the nature of the other interrupt's service routine.
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2.4
Processor Reset and Initialization
Processor initialization is accomplished with activation of the RST pin, which is the input to a Schmitt Trigger. To reset the processor, this pin should be held low for at least four machine cycles, while the oscillator is running stable. Upon powering up, RST should be held low for at least 10 ms after the power supply stabilizes to allow the oscillator to stabilize. Crystal operation below 6 MHz will increase the time necessary to hold RST low. Two machine cycles after receiving of RST, the processor ceases from instruction execution and remains dormant for the duration of the pulse. The high-going transition then initiates a sequence which requires approximately one machine cycle to execute before normal operation commences with the instruction at absolute location 0000H. Program memory locations 0000H through 0002H are reserved for the initialization routine of the microcomputer. This sequence ends with registers initialized as shown in chapter `Memory Organization'. After the processor is reset, all ports are written with one (1). Outputs are undefined until the reset period is complete. An automatic reset can be obtained when VDD is turned on by connecting the RST pin to VSS through a 10 F capacitor, providing the VDD rise time does not exceed a millisecond and the oscillator start-up time does not exceed 10 milliseconds. When power comes on, the current drawn by RST pin starts to charge the capacitor. The voltage VRST at RST pin is the capacitor voltage, and increases to VDD as the capacitor charges. The larger the capacitor, the more slowly VRST decreases. VRST must remain below the lower threshold of the Schmitt Trigger long enough to effect a complete reset. The time required is the oscillator start-up time plus 4 machine cycles.
Note: While reset is active and at least four machine cycles after rising edge of RST, ALE and P3.6 should not be pulled down externally. Otherwise a special production test mode is entered.
VDD
VDD
RST
VRST VSS
10 F
VSS
UES04722
Figure 18 Power-On Reset Circuit
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Power-Down Operations The controller provides two modes in which power consumption can be significantly reduced. - Idle mode. The CPU is gated off from the oscillator. All peripherals are still provided with the clock and are able to work. - Power-down mode. Operation of the controller is turned off. This mode is used to save the contents of internal RAM with a very low standby current. Both modes are entered by software. Special function register PCON is used to enter one of these modes. Power Control Register Default after reset: 00H (MSB) SMOD PDS IDLS PDE IDLE SMOD PDS IDLS - - - PDE (LSB) IDLE PCON SFR Address 87H
Power-down start bit. The instruction that sets the PDS-flag is the last instruction before entering the power down mode. IDLE start bit. The instruction that sets the PDS flag is the last instruction before entering the idle mode. Power-down enable bit. When set, starting the power-down mode is enabled. Idle enable bit. When set, starting the idle mode is enabled. Baud rate control for serial interface; if set, the baud rate is doubled.
The idle mode can be terminated by activation of any enabled interrupt (or a hardware reset). The CPU operation is resumed, the interrupt will be serviced and the next instruction to be executed after RETI instruction will be the one following the instruction that set the bit IDLS. The port state and the contents of SFRs are held during idle mode. The only exit from power-down mode is a hardware reset. The reset will redefine all SFRs, but will not change the contents of internal RAM.
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2.5
Ports and I/O-Pins
There are 24 I/O-pins configured as three 8-bit ports, 4 input lines (P2.4 ... 2.7) and one 2-bit port (P4.0 ... 4.1). Each I/O pin can be individually and independently programmed as input or output and each can be configured dynamically. An instruction that uses a port's bit/byte as a source operand reads a value that is the logical AND of the last value written to the bit/byte and the polarity being applied to the pin/pins by an external device (this assumes that none of the processor's electrical specifications are being violated). An instruction that reads a bit/byte, operates on the content, and writes the result back to the bit/byte, reads the last value written to the bit/byte instead of the logic level at the pin/pins. Pins comprising a single port can be made a mixed collection of inputs and outputs by writing a `one' to each pin that is to be an input. Each time an instruction uses a port as the destination, the operation must write `ones' to those bits that correspond to the input pins. An input to a port pin needs not to be synchronized to the oscillator. All the port latches have `one's written to them by the reset function. If a `zero' is subsequently written to a port latch, it can be reconfigured as an input by writing a `one' to it. The instructions that perform a read of, operation on, and write to a port's bit/byte are INC, DEC, CPL, JBC, SETB, CLR, MOV P.X, CJNE, DJNZ, ANL, ORL, and XRL. The source read by these operations is the last value that was written to the port, without regard to the levels being applied at the pins. This insures that bits written to a `one' (for use as inputs) are not inadvertently cleared. Port 0 has an open-drain output. Writing a `one' to the bit latch leaves the output transistor off, so the pin floats. In that condition it can be used as a high-impedance input. Port 0 is considered `true bidirectional', because when configured as an input it floats. Ports 1, 2.4 ... 2.7, 3 and 4 have `quasi-bidirectional' output drivers which comprise an internal pullup resistor. When configured as inputs they pull high and will source current when externally pulled low (see chapter 3.2). In ports 1, 2.4 ... 2.7, 3 and 4 the output drivers provide source current for one internal clock if, and only if, software updates the bit in the output latch from a ZERO to an ONE. Sourcing current only on `ZERO to ONE' transition prevents a pin, programmed as an input, from sourcing current into the external device that is driving the input pin.
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The following alternate functions can be selected when using the corresponding P3 pins: P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 INT0 INT1 T0 T1 RxD TxD (external interrupt 0) (external interrupt 1) (Timer/Counter 0 external input) (Timer/Counter 1 external input) (serial port receive line) (serial port transmit line)
Read-Modify-Write Feature `Read-modify-write' commands are instructions that read a value, possibly change it, and then rewrite it to the latch. When the destination operand is a port or a port bit, these instructions read the latch rather than the pin. The read-modify-write instructions are listed in table 3. The read-modify-write instructions are directed to the latch rather than the pin in order to avoid a possible misinterpretation of the voltage level at the pin. For example, a port bit might be used to drive the base of a transistor. When a ONE is written to the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather than the latch, it will read the base voltage of the transistor and interpret it as a 0. Reading the latch rather than the pin will return the correct value of ONE. Table 3 Read-Modify-Write Instructions Mnemonic ANL ORL XRL JBC CPL INC DEC DJNZ MOV PX.Y, C1) CLR PX.Y1) SETB PX.Y1)
1)
Description logical AND logical OR logical EX - OR jump if bit = `1' and clear bit complement bit increment decrement decrement and jump if not zero move carry bit to bit Y of Port X clear bit Y of Port X set bit Y of Port X
Example ANL P1, A ORL P2, A XRL P3, A JBC P1.1, LABEL CPL P3.0 INC P1 DEC P1 DJNZ P3, LABEL MOV P1.7, C CLR P2.6 SETB P3.5
The instruction reads the port byte (all 8 bits), modifies the addressed bit, then writes the new byte back to the latch.
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2.6
General Purpose Timers/Counters
Two independent general purpose 16-bit timers/counters are integrated for use in measuring time intervals, measuring pulse widths, counting events, and causing periodic (repetitive) interrupts. Either can be configured to operate as timer or event counter. In the `timer' function, the registers TLx and/or THx (x = 0, 1) are incremented every machine cycle. Thus, one can think of it as counting machine cycles. Since a machine cycle consists of 6 internal clocks, the count rate is 1/6 of the internal clock. In the `counter' function, the registers TLx and/or THx (x = 0, 1) are incremented in response to a 1-to-0 transition at its corresponding external input pin, T0 or T1. In this function, the external input is sampled during every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since it takes 2 machine cycles to recognize a 1-to-0 transition, the maximum count rate is 1/12 of the internal clock. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle. Timer/Counter 0: Mode Selection Timer/counter 0 can be configured in one of four operating modes, which are selected by bit-pairs (M1, M0) in TMOD-register (figure 19). - Mode 0 Putting timer/counter 0 into mode 0 makes it look like an 8048 timer, which is an 8-bit counter with a divide-by-32 prescaler. Figure 21 shows the mode 0 operation as it applies to timer 0. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1's to all 0's, it sets the timer interrupt flag TF0. The counted input is enabled to the timer when TR0 = `1' and either GATE = `0' or INT0 = `1'. (Setting GATE = `1' allows the timer to be controlled by external input INT0, to facilitate pulse width measurements.) TR0 is a control bit in the special function register TCON (figure 20). GATE is contained in register TMOD (figure 19).
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The 13-bit register consists of all 8 bits of TH0 and the lower 5 bits of TL0. The upper 3 bits of TL0 are indeterminate and should be ignored. Setting the run flag (TR0) does not clear the registers. - Mode 1 Mode 1 is the same as mode 0, except that the timer/counter 0 register is being run with all 16 bits. - Mode 2 Mode 2 configures the timer/counter 0 register as an 8-bit counter (TL0) with automatic reload, as shown in figure 22. Overflow from TL0 not only sets TF0, but also reloads TL0 with the contents of TH0, which is preset by software. The reload leaves TH0 unchanged. - Mode 3 Timer/counter 0 in mode 3 establishes TL0 and TH0 as two separate counters. The logic for mode 3 on timer 0 is shown in figure 23. TL0 uses the timer 0 control bits: C/T, GATE, TR0, INT0 and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 now controls the timer-1 interrupt. Mode 3 is provided for applications requiring an extra 8-bit timer or counter. With timer 0 in mode 3, the processor can operate as if it has three timers/counters. When timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of and into its own mode 3, or can still be used in any application not requiring an interrupt. Timer/Counter 1 Mode Selection Timer/counter 1 can also be configured in one of four modes, which are selected by its own bitpairs (M1, M0) in TMOD register. The serial port receives a pulse each time that timer/counter 1 overflows. This pulse rate is divided to generate the transmission rate of the serial port. Modes 0 and 1 are the same as for counter 0. - Mode 2 The `reload' mode is reserved to determine the frequency of the serial clock signal (not implemented). - Mode 3 When counter 1's mode is reprogrammed to mode 3 (from mode 0, 1, or 2), it disables the increment counter. This mode is provided as an alternative to using the TR1 bit (in TCON register) to start and stop timer/counter 1.
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Configuring the Timer/Counter Input The use of the timer/counter is determined by two 8-bit registers, TMOD (timer mode) and TCON (timer control), as shown in figure 19 and 20. The input to the counter circuitry is from an external reference (for use as a counter), or from the on-chip oscillator (for use as a timer), depending on whether TMOD's C/T-bit is set or cleared, respectively. When used as a time base, the internal clock is divided by six before being used as the counter input. When TMOD's GATE bit is set (1), the external reference input (T1, T0) or the oscillator input is gated to the counter conditional upon a second external input (INT0), (INT1) being high. When the GATE bit is ZERO (0), the external reference, or oscillator input, is unconditionally enabled. In either case, the normal interrupt function of INT0 and INT1 is not affected by the counter's operation. If enabled, an interrupt will occur when the input at INT0 or INT1 is low. The counters are enabled for incrementing when TCON's TR1 and TR0 bits are set. When the counters overflow, the TF1 and TF0 bits in TCON get set, and interrupt requests are generated. The counter circuitry counts up to all 1's and then overflows to either 0's or the reload value. Upon overflow, TF1 or TF0 is set. When an instruction changes the timer's mode or alters its control bits, the actual change occurs at the end of the instruction's execution. The T1 and T0 inputs are sampled near the falling-edge of ALE in the 5th, 11th, 17th and 23th internal clock of the instruction-in-progress. Thus, an external reference's high and low times must each be a minimum of 6 internal clock periods in duration. There is a 6 internal clock delay from the time when a toggled input (transition from high to low) is sampled to the time when the counter is incremented.
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Figure 19 Timer/Counter Mode Register Timer 0/1 Mode Register Default after reset: 00H (MSB) GATE C/T M1 M0 GATE C/T M1 (LSB) M0 TMOD SFR Address 89H
Timer 1
Timer 0
GATE Gating control when set. Timer/counter `x' is enabled only while `INTx' pin is HIGH and `TRx' control pin is set. When cleared, timer `x' is enabled, whenever `TRx' control bit is set. C/T Timer or counter selector. Cleared for timer operation (input from internal system clock). Set for Counter operation (input from `Tx' input pin). M0 0 1 0 1 Operating Mode SAB 8048 timer: `TLx' serves as five-bit prescaler. 16-bit timer/counter: `THx' and `TLx' are cascaded, there is no prescaler. 8-bit auto-reload timer/counter: `THx' holds a value which is to be reloaded into `TLx' each time it overflows. (Timer 0) TL0 is an eight-bit timer/counter controlled by the standard timer 0 control bits; TH0 is an eight-bit timer only controlled by timer 1 control bits. (Timer 1) timer/counter 1 is stopped.
M1 0 0 1 1
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Figure 20 Timer/Counter Control Register Timer 0/1 Control Register Default after reset: 00H (MSB) TF1 TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TR1 TF0 TR0 IE1 IT1 IE0 (LSB) IT0 TCON SFR Address 88H
Timer 1 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 1 run control bit. Set/cleared by software to turn timer/counter on/off. Timer 0 overflow flag. Set by hardware on timer/counter overflow. Cleared by hardware when processor vectors to interrupt routine. Timer 0 run control bit. Set/cleared by software to turn timer/counter on/off. Interrupt 1 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 1 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts. Interrupt 0 edge flag. Set by hardware when external interrupt edge detected. Cleared when interrupt processed. Interrupt 0 type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.
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.6 .
CDC = 0 Machine Cycles CDC = 1
OSC
. 12 .
C/T = 0 C/T = 1 T0 Pin Control
TL0 (5 Bits)
TH0 (8 Bits)
TF0
Interrupt
TR0 Gate INT0 Pin 1
_ <1
&
UES04602
Figure 21 Timer/Counter 0 Mode 0: 13-Bit Counter
. .6
CDC = 0 Machine Cycles CDC = 1
OSC
. 12 .
C/T = 0 C/T = 1 T0 Pin Control
TL0 (8 Bits)
TF0
Interrupt
TR0 Gate INT0 Pin 1
_ <1
&
Reload
TH0 (8 Bits)
UES04603
Figure 22 Timer/Counter 0 Mode 2: 8-Bit Auto-Reload
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. .6
CDC = 0 Machine Cycles CDC = 1
fm
OSC fm
. . 12
C/T = 0 C/T = 1 T0 Pin TR0 Gate INT0 Pin fm TR 1 Control 1
_ <1
TL0 (8 Bits) Control &
TF 0
Interrupt
TH0 (8 Bits)
TF1
Interrupt
UES04604
Figure 23 Timer/Counter 0 Mode 3: Two 8-Bit Counters
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2.7
Watchdog Timer
To protect the systems against software upset, the user's program has to clear this watchdog within a previously programmed time period. If the software fails to do this periodical refresh of the watchdog timer, an internal hardware reset will be initiated. The software can be designed so that the watchdog times out if the program does not work properly. The watchdog timer is a 15 bit counter with an 8 bit prescaler. Without the prescaler the counter is incremented every 12 internal clocks. If the prescaler is active the counter is incremented every 12 x 256 = 3072 internal clocks. The watchdog timer is initialized to the reload value programmed to WDTREL.6 ... WDTREL.0. After an external reset register WDTREL is cleared to 00H. The lower seven bits of WDTREL can be loaded by software at any time. The watchdog timer is started by software by setting bit SWDT in special function register WDCON (bit 6). If the counter is stopped, and WDTREL is loaded with a new value, WDTH (high-byte of the watchdog timer) is updated immediately. WDTL (low-byte of the watchdog timer) is always zero, if the counter is stopped. Once started the watchdog timer cannot be stopped by software but can only be refreshed to the reload value by first setting bit WDT (WDCON.2) and by the next instruction setting SWDT (WDCON.6). Bit WDT will automatically be cleared during the third machine cycle after having been set. This double instruction refresh of the watchdog timer is implemented to minimize the chance of an unintentional reset of the watchdog. If the software fails to clear the watchdog in time, an internally generated watchdog reset is entered at the counter state 7FFCH. The duration of the reset signal then depends on the prescaler selection. This internal reset differs from an external reset only in so far as the watchdog timer is not disabled and bit WDTS (WDCON.7) is set. Bit WDTS allows the software to examine from which source the reset was activated. The watchdog timer status flag can also be cleared by software. With WDTREL = 80H a maximum time period of about 8 s at 12 MHz internal clock can be achieved.
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Watchdog Timer Control Register Default after reset: 0XXX XXXXB (MSB) WDTS SWDT - -
WDCON
SFR Address A7H
(LSB) - WDT - -
WDTS Watchdog timer status flag: If bit WDTS is `1' after reset, the reset has been initialized by the watchdog timer. After external reset, WDTS is reset to `0'. This bit can be written by software too. SWDT Start watchdog timer: A write to WDCON with SWDT= `1' and WDT= `0' starts the WDT operation. WDT Watchdog timer refresh flag: A write to WDCON with WDT= `1' and SWDT= `0' initialize a refresh cycle. The next write to WDCON must follow immediately with WDT= `0' and SWDT = `1' to execute the refresh cycle.
Note: SWDT and WDT can only be written, so read-modify-write opcodes are not useful.
Watchdog Timer Reload Register Default after reset: 00H (MSB) Bit 7 WDTREL.7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 WDTREL SFR Address 86H
Prescaler bit. When set, the watchdog is clocked through an additional divide by 256 prescaler.
WDTREL.0 ... WDTREL.6 Seven bit reload value for the high-byte of the watchdog timer. This value is loaded to the WDT when a refresh is triggered by a consecutive setting of bits WDT and SWDT.
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Watchdog High Byte Default after reset: 80H (MSB) - WDTH.7 Bit 6 Bit 5
WDTH
SFR Address 85H
(LSB) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Not implemented.
WDTH.6 ... 0 These are the upper 7 bits of the 15 bit watchdog counter. These bits are only readable. Watchdog Low Byte Default after reset: 00H (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 WDTL SFR Address 84H
Bit 7 ... Bit 0 These are the lower 8 bits of the 15 bit watchdog counter. They are only readable.
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2.8
Serial Interface
The serial port is full duplex, meaning it can transmit and receive simultaneously. It is also receive-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register (however, if the first byte still hasn't been read by the time reception of the second byte is complete, one of the bytes will be lost). The serial port receive and transmit registers are both accessed at special function register SBUF. Writing to SBUF loads the transmit register, and reading SBUF accesses a physically separate receive register. The frequencies and baud rates described in this chapter depend on the internal clock, used by the serial interface. The serial port can operate in 4 modes: Mode 0: Mode 1: Serial data enters and exits through RxD (P3.6). TxD (P3.7) outputs the shift clock at 1/6 of the internal clock. 10 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB8 in special function register SCON. The baud rate is variable. 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (1). On transmission, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. On reception, the 9th data bit goes into RB8 in the special function register SCON, while the stop bit is ignored. The baud rate is programmable to either 1/16 or 1/32 of the internal clock. 11 bits are transmitted (through TxD) or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit and a stop bit (1 ). In fact, mode 3 is the same as mode 2 in all respects except the baud rate. The baud rate in mode 3 is variable.
Mode 2:
Mode 3:
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Figure 24 Serial Port Control Register SCON Serial Port Control Register Default after reset: 00H (MSB) SM0 9FH SM1 9EH SM2 9DH REN 9CH TB8 9BH RB8 9AH TI 99H (LSB) RI 98H Bit Address SCON SFR Address 98H
Symbol Position Function SM0 SM1 SM2 SCON.7 Serial Port Mode Selection, see table 4. SCON.6 SCON.5 Enables the multiprocessor communication feature in modes 2 and 3. In mode 2 or 3, if SM2 is set to `1' then RI will not be activated if the received 9th data bit (RB8) is 0. In mode 1, if SM2 = `1' then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be `0'. SCON.4 Enables serial reception. Set by software to enable reception. Cleared by software to disable reception. SCON.3 Is the 9th data bit that will be transmitted in modes 2 and 3. Set or cleared by software as desired. SCON.2 In modes 2 and 3, is the 9th data bit that was received. In mode 1, if SM2 = `0', RB8 is the stop bit that was received. In mode 0, RB8 is not used. SCON.1 Is the transmit interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. SCON.0 Is the receive interrupt flag. Set by hardware at the end of the 8th bit time in mode 0, or halfway through stop bit time in the other modes, in any serial reception. Must be cleared by software.
REN TB8 RB8
TI
RI
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Table 4 Serial Port Mode Selection SM0 0 0 1 1 SM1 0 1 0 1 Mode 0 1 2 3 Description Shift Reg. 8-bit UART 9-bit UART 9-bit UART Baud Rate Internal clock / 6 Variable Internal clock / 16 or 32 Variable
In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in mode 0 by the condition Rl = `0' and REN = `1'. Reception is initiated in the other modes by the incoming start bit if REN = `1'. The control, mode, and status bits of the serial port in special function register SCON are illustrated in figure 24. 2.8.1 Multiprocessor Communication
Modes 2 and 3 of the serial interface of the controller have a special provision for multiprocessor communication. In these modes, 9 data bits are received. The 9th one goes into RB8. Then comes a stop bit. The port can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = `1'. This feature is enabled by setting bit SM2 in SCON. A way to use this feature in multiprocessor communications is as follows. When the master processor wants to transmit a block of data to one of the several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is `1' in an address byte and 0 in a data byte. With SM2 = `1', no slave will be interrupted by a data byte. An address byte however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that will be coming. The slaves that weren't addressed leave their SM2s set and go on about their business, ignoring the coming data bytes. SM2 has no effect in mode 0, and in mode 1 can be used to check the validity of the stop bit. In a mode 1 reception, if SM2 = `1', the receive interrupt will not be activated unless a valid stop bit is received.
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2.8.2
Baud Rates
For the following calculations fint is equal to the internal clock. The baud rate in mode 0 is fixed: Mode 0 baud rate =
fint
6
The baud rate in mode 2 depends on the value of bit SMOD in special function register PCON (bit 7). If SMOD = 0 (which is the value on reset), the baud rate is 1/32 of the internal clock. If SMOD = `1', the baud rate is 1/16 of the internal clock. Contrary to the SAB 8051 SMOD is placed on SFR address 87H. Mode 2 baud rate = 2SMOD 32 x fint
The baud rates in modes 1 and 3 are determined by the timer 1 overflow rate or can be generated by the internal baud rate generator. When timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of SMOD as follows: Modes 1, 3 baud rate = 2SMOD 16 x Time 1 overflow rate
The timer 1 interrupt should be disabled in this application. The timer itself can be configured for either `timer' or `counter' operation, and in any of the 3 running modes. In the most typical applications, it is configured for `timer' operation, in the auto-reload mode (high nibble of TMOD = 0010B). In that case, the baud rate is given by the formula: Modes 1, 3 baud rate = 2SMOD 32 x
fint
6 x (256 - TH1)
One can achieve very low baud rates with timer 1 by leaving the timer 1 interrupt enabled, configuring the timer to run as a 16-bit timer (high nibble of TMOD = 0001B), and using the timer 1 interrupt to do a 16-bit software reload. Table 5 lists various commonly used baud rates and how they can be obtained from timer 1.
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Table 5 Generated Commonly Used Baud Rates Baud Rate
fINT
[MHz]
SMOD CT X 1 1 1 0 0 0 0 0 0 0 X X 0 0 0 0 0 0 0 0 0
Timer 1 Mode X X 2 2 2 2 2 2 2 2 1 Reload Value X X FFH FDH FDH FAH F4H E8H 1DH 72H FEEBH
Mode 0 max: Mode 2 max: Mode 1, 3:
2 MHz 750 Kbaud
12.0 12.0
62.5 Kbaud 6.0 19.2 Kbaud 5.529 9.6 Kbaud 4.8 Kbaud 2.4 Kbaud 1.2 Kbaud 110 Baud 110 Baud 5.529 5.529 5.529 5.529 3.0 6.0
137.5 Baud 5.993
2.8.3
More about Mode 0
Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are transmitted/ received: 8 data bits (LSB first). The baud rate is fixed at 1/6 of the internal frequency. Figures 25a and 25b show a simplified functional diagram of the serial port in mode 0, and associated timing. Transmission is initiated by any instruction that uses SBUF as a destination register. The `write-to SBUF' signal also loads a `1' into the 9th bit position of the transmit shift register and tells the TX-control block to commence a transmission. The internal timing is such that one full machine cycle will elapse between `write-to-SBUF' and activation of SEND.SEND enables the output of the shift register to the alternate output function line of P3.6, and also enables SHIFT CLOCK to the alternate output function, line of P3.7. SHIFT CLOCK is low during S3, S4 and S5 of every machine cycle, and high during S6, S1, and S2 (Sx = internal state x of one machine cycle). At state 6 of every machine cycle in which SEND is active, the contents of the transmit shift register is shifted one position to the right. As data bits shift out to the right, zeros come in from the left. When the MSB of the data byte is at the output position of the shift register, then the `1' that was initially loaded into the 9th position, is just left of the MSB, and all positions to the left of that contain zeros.
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This condition flags the TX-control block to do one last shift and then deactivate SEND and set Tl. Both of these actions occur in the 10th machine cycle after `write-to-SBUF'. Reception is initiated by the condition REN = `1' and Rl = `0'. At state 6 in the next machine cycle, the RX-control unit writes the bits 1111 1110 to the receive shift register, and the next clock phase activates RECEIVE. RECEIVE enables SHIFT CLOCK to the alternate output function line of P3.7. SHIFT CLOCK makes transitions at state 3 and state 6 in every machine cycle. At state 6 of every machine cycle in which RECEIVE is active, the contents of the Receive Shift register are shifted one position to the left. The value that comes in from the right is the value that was sampled at the P3.6 pin at state 5 in the same machine cycle. As data bits come in from the right, 1 s shift out to the left. When the 0 that was initially loaded into the rightmost position arrives at the leftmost position in the shift register, it flags the RX-control block to do one last shift and load SBUF. At state 1 in the 10th machine cycle after the write to SCON that cleared Rl, RECEIVE is cleared and Rl is set. 2.8.4 More about Mode 1
Ten bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first) and a stop bit (1). On reception, the stop bit goes into RB8 in SCON. The baud rate is determined by the timer 1 overflow rate. Figures 26a and 26b shows a simplified functional diagram of the serial port in mode 1, and associated timings for transmit and receive. Transmission is initiated by any instruction that uses SBUF as a destination register. The `write-to SBUF' signal also loads a 1 into the 9th bit position of the transmit shift register and flags the TX- control block that a transmission is requested. Transmission actually commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the `write-to-SBUF' signal). The transmission begins with activation of SEND, which puts the start bit to TxD. One bit time later, DATA is activated, which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. As data bits shift out to the right, zeros are clocked in from the left. When the MSB of the data byte is at the output position of the shift register, then the 1 that was initially loaded into the 9th position is just left of the MSB, and all positions to the left of that contain zeros. This condition flags the TX-control unit to do one last shift and then deactivate SEND and set Tl. This occurs at the 10th divide-by-16 rollover after `write-to-SBUF'. Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1 FFH is written into the input shift register. Resetting the divide-by-16 counter aligns its rollovers with the boundaries of the incoming bit times.
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The 16 states of the counter divide each bit time into 16ths. At the 7th, 8th and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back looking for another 1-to-0 transition. This is to provide rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1 s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in mode 1 is a 9-bit register), it flags the RX-control block to do one last shift, load SBUF and RB8, and set Rl. The signal to load SBUF and RB8, and to set Rl, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1) Rl = 0, and 2) either SM2 = 0 or the received stop bit = 1 If either of these two conditions is not met, the received frame is irretrievably lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF and Rl is activated. At this time, no matter whether the above conditions are met or not, the unit goes back looking for a 1-to-0-transition in RxD. 2.8.5 More about Modes 2 and 3
11 bits are transmitted (through TxD), or received (through RxD): a start bit (0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit, (1). On transmission, the 9th data bit (TB8) can be assigned the value of 0 or 1. On reception, the 9th data bit goes into RB8 in SCON. The baud rate is programmable to either 1/32 or 1/64 of the oscillator frequency in mode 2. Mode 3 may have a variable baud rate generated from timer 1. Figures 27a, 27b and 28a, 28b show a functional diagram of the serial port in modes 2 and 3 and associated timings. The receive portion is exactly the same as in mode 1. The transmit portion differs from mode 1 only in the 9th bit of the transmit shift register. Transmission is initiated by any instruction that uses SBUF as a destination register. The `write-to- SBUF' signal also loads TB8 into the 9th bit position of the transmit shift register and flags the TX- control unit that a transmission is requested. Transmission commences at S1P1 of the machine cycle following the next rollover in the divide-by-16 counter (thus, the bit times are synchronized to the divide-by-16 counter, not to the `write-to-SBUF' signal). The transmission begins with activation of SEND, which puts the start bit to TxD. One bit time later, DATA is activated which enables the output bit of the transmit shift register to TxD. The first shift pulse occurs one bit time after that. The first shift clocks a 1 (the stop bit) into the 9th bit position of the shift register. Thereafter, only zeros are clocked in. Thus, as data bits shift out to the right, zeros are clocked in from the left. When TB8 is
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at the output position of the shift register, then the stop bit is just left of the TB8, and all positions to the left of that contain zeros. This condition flags the TX-control unit to do one last shift and then deactivate SEND and set Tl. This occurs at the 11th divide-by-16 rollover after `write-to-SBUF'. Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is sampled at a rate of 16 times whatever baud rate has been established. When a transition is detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift register. At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. If the value accepted during the first bit time is not 0, the receive circuits are reset and the unit goes back looking for another 1-to-0 transition. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed. As data bits come in from the right, 1 s shift out to the left. When the start bit arrives at the leftmost position in the shift register (which in modes 2 and 3 is a 9-bit register), it flags the RX-control block to do one last shift, load SBUF and RB8, and set Rl. The signal to load SBUF and RB8, and to set Rl, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: 1) Rl = 0, and 2) either SM2 = 0 or the received 9th data bit = 1 If either of these two conditions is not met, the received frame is irretrievably lost, and Rl is not set. If both conditions are met, the received 9th data bit goes into RB8, the first 8 data bits go into SBUF. One bit time later, no matter whether the above conditions are met or not, the unit goes back looking for a 1-to-0-transition at the RxD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8 or Rl.
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Internal Bus 1
Write to SBUF D S Q & SBUF
RxD P3.6 Alt. Output Function
CL
Shift Zero Detector
Start TX Control Clock TX Clock Serial Port Interrupt
_ <1
TI
Send
_ <1
&
TxD P3.7 Alt. Output Function
Shift Clock RI RX Control Receive
REN RI
& Start RX Clock
1 1 1 1 1 1 1 0 Shift RxD P3.6 Alt. Input Function
Input Shift Register Load SBUF Shift
SBUF Read SBUF Internal Bus
UES04726
Figure 25a Serial Port Mode 0, Functional Diagram
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Figure 25b Serial Port Mode 0, Timing
Write to SBUF Send
Transmit
Shift RxD (Data Out) TxD (Shift Clock) TI Write to SCON (Clear RI) RI D0 D1 D2 D3 D4 D5 D6 D7
SDA 30C263 / SDA 30C264
Receive
Receive Shift D0 RxD (Data In) TxD (Shift Clock) D1 D2 D3 D4 D5 D6 D7
UED04727
SDA 30C263 / SDA 30C264
Internal Bus 1
Write to SBUF D S Q & SBUF
_ <1
TxD
CL
Zero Detector
Start Timer1 Overflow SMOD=1
Shift TX Control
Data Send
. . 16
TX Clock Serial Port Interrupt
_ <1
TI
. .2
SMOD=0 (PCON.7) Sample 1-to-0 Transition Detector
. 16 .
RX Clock Start RX Control RI Load SBUF
1FFH Shift Bit Detector RxD Load SBUF
Input Shift Register (9 Bits) Shift
SBUF Read SBUF Internal Bus
UES04728
Figure 26a Serial Port Mode 1, Functional Diagram
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TX Clock
Semiconductor Group
Transmit
D0 D1 D2 D4 D7 D3 D5 D6 Stop Bit / 16 Reset Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit
UED04729
Write to SBUF
Send
Figure 26b Serial Port Mode 1, Timing
Data
Shift
TxD
Start Bit
TI
73
RX Clock
RxD
Receive
Bit Detector Sample Times
Shift
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Internal Bus TB8
Write to SBUF S D CL Zero Detector Q SBUF &
_ <1
TxD
Phase 2 CLK SMOD=1
Stop Bit Gen. Shift Start TX Control
Data Send
. 16 .
TX Clock Serial Port Interrupt
_ <1
TI
.2 .
SMOD=0 (PCON.7) Sample 1-to-0 Transition Detector
. 16 .
RX Clock Start RX Control RI Load SBUF
1FFH Shift Bit Detector RxD Load SBUF
Input Shift Register (9 Bits) Shift
SBUF Read SBUF Internal Bus
UES04730
Figure 27a Serial Port Mode 2, Functional Diagram
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Figure 27b Serial Port Mode 2, Timing
TX Clock Write to SBUF Send
Transmit
Data Shift TxD TI Stop Bit Gen. / 16 Reset RX Clock RxD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop Bit
SDA 30C263 / SDA 30C264
Receive
Bit Detector Sample Times Shift RI
UED04731
SDA 30C263 / SDA 30C264
Internal Bus TB8
Write to SBUF D S Q & SBUF
_ <1
TxD
CL
Zero Detector
Start Timer1 Overflow SMOD=1
Shift TX Control
Data Send
. 16 .
TX Clock Serial Port Interrupt
_ <1
TI
.2 .
SMOD=0 (PCON.7) Sample 1-to-0 Transition Detector
. . 16
RX Clock Start RX Control RI Load SBUF
1FFH Shift Bit Detector RxD Load SBUF
Input Shift Register (9 Bits) Shift
SBUF Read SBUF Internal Bus
UES04732
Figure 28a Serial Port Mode 3, Functional Diagram
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Figure 28b Serial Port Mode 3, Timing
TX Clock Write to SBUF Send
Transmit
Data Shift TxD TI / 16 Reset RX Clock RxD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 RB8 Stop Bit Start Bit D0 D1 D2 D3 D4 D5 D6 D7 TB8 Stop Bit
SDA 30C263 / SDA 30C264
Receive
Bit Detector Sample Times Shift RI
UED04733
SDA 30C263 / SDA 30C264
2.9
Pulse Width Modulation Unit
The PWM unit provides eight independent digital to analog conversion channels: six output channels with 8 bit resolution and two output channels with 14 bit resolution. Controlled via special function registers, each channel can be enabled individually. The base frequency of each channel depends on its resolution. The 8 bit channels have a cycle time of 64 internal clocks. The 14 bit channels have a cycle time of 256 internal clocks. For an internal clock of 8 MHz, this results in 187 kHz output frequency for 8 bit channels and 47 kHz for 14 bit channels. The 8 bit channels use the 6 most significant bits of PWCOMPx for generating the base high/low ratio of the output signal. With the 2 least significant bits of PWCOMPx the high/low ratio is modified for an overall resolution of 8 bits. The 14 bit channels use PWCOMPx for generating the base high/low ratio of the output signal. With the 6 most significant bit of PWEXTx the high/low ratio is modified for an overall resolution of 14 bits. General Considerations The PWM output channels are placed as alternate functions to the eight lines of port 1. P1.0 ... P1.5 contain the 6 output channels with 8-bit resolution and P1.6 ... P1.7 the 2 output channels with 14-bit resolution. Each PWM channel can be individually switched between PWM function and port function. The six 8-bit compare registers PWCOMP0 ... PWCOMP5 are located at SFR addresses 0F1H ... 0F6H. The two 14-bit compare registers consist each of an 8-bit register PWCOMP6 or PWCOMP7 and of a six-bit extension register PWEXT6 or PWEXT7, all located at SFR addresses 0FAH ... 0FDH. They contain the modulation ratios of the output signals, which are related to the maximum, defined by the counter's resolution. These compare registers are double buffered and a new compare value will only be taken into the main register after the next timer overflow or if the PWM timer is stopped. The PWM timer register located at SFR address F7H and F9H contain the actual value of the PWM counter low byte and high byte and can only be read by the CPU. Every compare register, which is not employed for the PWM output can be used as an additional register. This is not allowed for register PWME. The internal timer of the PWM unit is running as long as at least one PWM channel is enabled by the PWM Enable Register PWME. At timer overflow of the 8-bit [14-bit] timer, all output latches OL0 ... OL5 [OL6 and OL7] are set to `1'. If the timer value meets the compare value of channel i, OLi is reset to `0'.
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PWM Enable Register Default after reset: 00H (MSB) E7 E7 ... E0 E6 E5
PWME
SFR Address F8H
(LSB) E4 E3 E2 E1 E0
`0': The corresponding PWM channel is disabled. P1.i functions as normal bidirectional I/O-port. `1': The corresponding PWM channel is enabled. E0...E5 are channels with 8-bit resolution, while E6 and E7 are channels with 14-bit resolution. PWCOMP0 ... 5 SFR Address F1H ... F6H
PWM Compare Registers Default after reset: 00H (MSB) Bit 7 Bit 6 Bit 5
(LSB) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 ... Bit 2 These bits define the high time of the output. If all bits are `0', the high time is 0 internal clocks. If all bits are `1', the high time is 63 internal clocks. Bit 1 Bit 0 If this bit is set, every second PWM Cycle is stretched by one internal clock, regardless of the settings of Bit 7 ... Bit 2. If this bit is set, every fourth PWM Cycle is stretched by one internal clock, regardless of the settings of Bit 7 ... Bit2.
Note: The stretch operation is interleaved between PWM Cycles.
PWM Compare Registers Default after reset: 00H (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 PWCOMP6, 7 SFR Address FBH, FDH
Bit 7 ... Bit 0 These bits define the high time of the output. If all bits are `0', the high time is 0 internal clocks. If all bits are `1', the high time is 255 internal clocks.
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PWM Extension Registers Default after reset: 02H (MSB) Bit 7 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1, Bit 0 Bit 6 Bit 5
PWEXT 6, 7
SFR Address FAH, FCH
(LSB) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
If this bit is set, every second PWM Cycle is stretched by one internal clock. If this bit is set, every fourth PWM Cycle is stretched by one internal clock. If this bit is set, every eighth PWM Cycle is stretched by one internal clock. If this bit is set, every 16th PWM Cycle is stretched by one internal clock. If this bit is set, every 32th PWM Cycle is stretched by one internal clock. If this bit is set, every 64th PWM Cycle is stretched by one internal clock. These bits must always be set to `0'.
Note 1: The described operation is independent of the setting of PWCOMP6 or PWCOMP7. Note 2: The stretch operation is interleaved between PWM Cycles.
PWM Low Counter Registers Default after reset: 00H (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 (LSB) Bit 0 PWCL SFR Address F7H
Bit 7 ... Bit 0 These bits are the low order 8 Bits of the 14 Bit PWM Counter. This register can only be read.
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PWM High Counter Registers Default after reset: C0B (MSB) Bit 7 Bit 7, Bit 6: Bit 6 Bit 5
PWCH
SFR Address F9H
(LSB) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
These bits are undefined.
Bit 5 ... Bit 0: These bits are the high order 6 Bits of the 14 Bit PWM Counter. This register can only be read. 2.10 Analog Digital Converter
The controller provides an A/D-converter with the following features: - 4 multiplexed input channels, which can also be used as digital inputs - 8-bit resolution - 6.7 to 21.3 s conversion time at 12 MHz internal clock The conversion time depends on the internal clock and the setting of PSC and SAMP in ADCON. If PSC and SAMP are `0', the sample period is 16 internal clocks and the approximation time is 64 internal clocks. If SAMP is set to `1' the sample time is increased fourfold to 64 internal clocks. If PSC is set to `1' the selected sample time and the approximation time are doubled. For the conversion, the method of successive approximation via capacitor array is used. There are three user accessable special function registers: ADCON, ADDAT and DAPR. Special function register ADCON is used to set the operation modes, to check the status and to select one of four input channels. ADCON contains two mode bits. Bit ADM is used to choose the single or continuous conversion method. In single conversion mode (ADM = `0') only one conversion is performed after starting, while in continuous conversion mode (ADM = `1') after the first start a new conversion is automatically started on completion of the previous one. The busy flag BSY (ADCON.4) is automatically set when a conversion is in progress. After completion of the conversion it is reset by hardware. This flag can be read only, a write has no effect. MX0 and MX1 are used to select one of 4 A/D-channels. The special function register ADDAT holds the converted digital 8-bit data result. The data remains in ADDAT until it is overwritten by the next converted data. A new conversion can be started only after reading ADDAT. ADDAT can be read or written under software control. A start of conversion is triggered by a write-to DAPR instruction. The data written must be 00H.
Semiconductor Group
81
1996-06-01
SDA 30C263 / SDA 30C264
ADC Start Register Default after Reset: XXH (MSB) - - - -
DAPR
SFR Address DAH
(LSB) - - - -
Only the address of DAPR is used to decode a start-of-conversion signal. No bits are implemented. A read from DAPR shows random values. ADC Control Register Default after reset: 00H (MSB) PSC SAMP - BSY ADM 0 MX1 (LSB) MX0 ADCON SFR Address D8H
This register is bit addressable. PSC Prescaler control: PSC = `0' for prescaler not active, internal master clock of the ADC is equal to the internal clock. PSC = `1' for prescaler active, internal master clock of ADC is half of the internal clock. SAMP ADCON.5 ADCON.2 BSY ADM MX1, MX0 MX1 0 0 1 1 Sample time: If SAMP= `1' the sample time is 64 internal clocks, if SAMP = `0' the sample time is 16 internal clocks. Reserved Always to be written with `0' Busy flag: BSY = `1' during conversion ADC conversion mode: ADM = `0' for single and ADM = `1' for continuous conversion. ADC channel select MX0 0 1 0 1 Selected Channel 0 1 2 3
Note: After changing the input channel, the input signal has to stabilize before a new conversion is started.
Semiconductor Group
82
1996-06-01
SDA 30C263 / SDA 30C264
ADC Data Register Default after reset: XXH (MSB) AD7 ADDAT.7-.0 2.10.1 AD6 AD5
ADDAT
SFR Address D9H
(LSB) AD4 AD3 AD2 AD1 AD0
8-Bit Analog Data Value
Analog Detector (SDA 30C264 only)
The ADC contains special logic to simplify the task of supervising an analog voltage. For this purpose, several registers are implemented. Detector-Control Register Default after reset: 0000 0XXXB (MSB) OV OV UN DECON.5 REQ END TI2, TI1, TI0 TI2 0 0 0 0 1 1 1 1 UN 0 REQ END TI2 TI1 (LSB) TI0 DECON SFR Address DCH
OVERFLOW - Flag: OV = `1' if DEUP - ADDAT < 0. UNDERFLOW - Flag: UN = `1' if ADDAT - DELOW < 0. Always to be written with `0' Request Flag: REQ = `1' if CPU conversion request is pending. Reset to `0' after start of conversion. Enable Detector: if END = `1' the detector is active. Timing Intervall select TI1 0 0 1 1 0 0 1 1 TI0 0 1 0 1 0 1 0 1 Selected Timing Intervall in Internal Machine Cycles 512 1024 2048 4096 8192 16384 32768 65536
83 1996-06-01
Semiconductor Group
SDA 30C263 / SDA 30C264
Detector-Select Register Default after reset: undefined (MSB) - DESEL.7-.2 DX1, DX0 DX1 0 0 1 1 Detector-Lower Register Default after reset: undefined (MSB) DL7 DELOW.7-.0 DL6 DL5 - -
DESEL
SFR Address DDH
(LSB) - - - DX1 DX0
Reserved, to be set to 0 ADC channel select for monitoring DX0 0 1 0 1 DELOW Selected Channel 0 1 2 3 SFR Address DEH
(LSB) DL4 DL3 DL2 DL1 DL0
8-Bit lower Limit DEUP SFR Address DFH
Detector-Upper Register Default after reset: undefined (MSB) DU7 DEUP.7-.0 DU6 DU5
(LSB) DU4 DU3 DU2 DU1 DU0
8-Bit upper Limit
Semiconductor Group
84
1996-06-01
SDA 30C263 / SDA 30C264
Operation Description (SDA 30C264 only) The detector implements an `out-of-range' supervising function. This can be used to avoid software polling of the ADC in certain applications. 4 registers are available to control the detector. The lower 2 bits of DESEL select the input channel for the detector independent of MX1 and MX0 in ADCON. The input switch is done automatically. After the detector cycle has finished, MX1 and MX0 control the input channel again. DEUP holds the upper limit, DELOW holds the lower limit. The register DECON contains status and control bits. OV and UN are updated by hardware at the end of a detector cycle. OV is set to `1' if DEUP - ADDAT< 0. UN is set to `1' if ADDAT - DELOW < 0. All values are interpreted as zero-extended integers. The flags can be set and reset by software, too. END enables the detector. TIx selects one of 8 timing intervals. After each timing intervall a request for conversion is generated. The detector has its own 16 bit counter, which is incremented every machine cycle. The operation-sequence starts after the selected timing interval. The ADC starts a conversion of the channel selected by DESEL. If a conversion is in progress, the detector-request will be stored and serviced after the CPU has read ADDAT. This insures that the CPU has received the result of the conversion. The result of the detector cycle is stored in ADDAT. Now the comparator operations are performed and the corresponding flags are set or reset. An interrupt is generated if EAD is set to `1' in IE and OV or UN is `1'. During the detector cycle the BSY bit is set to show that a conversion is in progress. If the CPU makes a request for conversion during this time, the request will be stored and serviced after the running conversion. The bit REQ in DECON shows the pending CPU request. It is automatically cleared after the conversion has started. The request can be cancelled, if REQ is set to `0'. If an `out-of-range' value is detected, the detector will disable further conversions until the processor has cleared the bits OV and UN. This prevents overwriting of ADDAT until the CPU has checked the value, under the assumption that a conversion request is pending. If DELOW is set to `0', an underflow is impossible. If DEHI is set to 255, an overflow is impossible. If DELOW = DEHI a certain value can be supervised. (This implies noise-limited analog signals!)
Semiconductor Group
85
1996-06-01
SDA 30C263 / SDA 30C264
2.11
I2C Serial Interface (SDA 30C264 only)
The I2C serial interface has been designed to satisfy the multi-master requirements of the I2C Bus Specification. All enhancements like 10 bit addressing and 400 kbit/s data rate are included. This interface detects, receives and converts the serial data stream to parallel format without interrupting the execution of the current program. An interrupt request is generated when the complete byte has been received; the microcomputer can then read the data byte in a single instruction. Likewise, for transmission, the serial interface performs the parallel to serial conversion and subsequent serial output of the data while the microcomputer continues with execution of its programmed tasks. After completion of the transmission an interrupt is generated. The interface also provides simple mechanisms for acknowledgment of data reception. The serial interface works with a serial bus consisting of two bi-directional lines SDA and SCL: one for data signals and one for clock signals, respectively. A protocol has been defined to allow reliable and efficient operation of this bus. During data transfer, the SDA line must remain stable whenever the SCL line is high. Changes of the SDA line while the SCL line is high will be interpreted as control signals. Accordingly, the following bus conditions have been defined: a) b) c) d) Bus not busy: both SDA and SCL lines remain high. Start data transfer: a change in the state of the SDA line, from high to low, while the SCL line is high, defines the start condition. Stop data transfer: a change in the state of the SDA line, from low to high, while the SCL line is high, defines the stop condition. Data valid: the state of the SDA line represents valid data when, after a start condition, the SDA line is stable for the duration of the high period of the clock signal. The data on the line may be changed during the low period of the clock signal. There is one clock pulse per bit of data.
Figure 29 illustrates the sequence of events involved in data transfer on the serial bus. Each data transfer is initiated with a start condition and terminated with a stop condition; the number of bytes transferred between the start and stop conditions is not limited; one byte consists of eight bits. 2.11.1 Registers and Hardware-Interface
The I2C interface in the SDA 30C264 has multiple operation options. Two complete SDA/SCL line pairs are available: channel 0 and channel 1. In a special mixed mode, one SCL line could be shared for both SDA lines. The advantage of such an arrangement is that more addresses are available and different speeds can be used, one interface with 100 kbit/s original specification, the other with the new 400 kbit/s specification. Therefore the baud rate for each channel is programmable. A total of 6 registers is available for the programmer.
Semiconductor Group 86 1996-06-01
SDA 30C263 / SDA 30C264
I2C Control Register Default after reset: 0000 0X00B (MSB) SLA TRX BB
ICCON
SFR Address B8H
(LSB) IIN AL LRB ACK BUM
This register is bit addressable. SLA Slave: If SLA = `1' the interface is active as a slave on the selected bus. SLA is set to `1' after receiving the correct device address. SLA is reset to `0' after a stop condition. SLA = `0' has two meanings: 1. the bus is not busy or 2. the interface is in master mode. Transmit select: In all modes, TRX = `1' selects transmission of data, TRX = `0' selects reception of data. Bus Busy: This bit can only be read. If the I2C interface is active, this bit monitors the I2C Bus status. After a start condition on the selected I2C Bus, BB is set to `1'. After a stop condition on the selected I2C Bus, BB is reset to `0'. If the I2C interface is inactive, this bit is always `0'. I2C Interrupt: After transmitting or receiving the acknowledge bit, IIN is set to `1'. If the state of SLA or AL changes from `0' to `1' IIN is also set to `1'.IIN can be set or reset by software.If IIN is `1' and the device is master or selected as a slave SCL is held low. Resetting IIN to `0' releases SCL and starts a data transmission. Arbitration lost: If this bit is set, the interface has tried to become a master on the bus, but has lost the arbitration. The interface continues operation until the 9th clock pulse. IIN is set after the 9th clock pulse. Software has to reset this bit to `0'. Last received bit: If the interface is in transmitter mode, this bit represents the acknowledge bit of the receiver of the last transmission. Acknowledge Pulse: If the interface is in the receiver mode and ACK = `0', an acknowledge pulse is generated; if ACK = `1', no pulse is generated. Busy Master: in master or multimaster mode this bit can be set to `1'. Otherwise it is always `0'. A 0-to-1 transition of BUM generates a start condition, a 1-to-0 transition generates a stop condition. If BB = `1' and BUM is set to `1' an arbitration lost situation occurs. BUM is reset to `0' and AL is set to `1'.
TRX BB
IIN
AL
LRB ACK BUM
Semiconductor Group
87
1996-06-01
SDA 30C263 / SDA 30C264
I2C Mode Register Default after reset: 000X 00XXB (MSB) CSEL CSEL EMA ES
ICMOD
SFR Address B9H
(LSB) ADR RSC M10 ICA9 ICA8
Channel select: CSEL = `0' selects channel 0 for the following operation, CSEL = `1' selects channel 1. Enable Master Mode: see table below for definition of operation modes. Enable Slave Mode: see table below for definition of operation modes. Address: After a start condition the first byte in 8 bit mode is the address and ADR is set to `1'. In 10 bit mode the first two bytes received have ADR set to `1'. Repeated Start Condition: If the interface is active as a master, setting this bit generates a repeated start condition. RSC is automatically reset to `0' after sending the repeated start condition. RSC can not be set in slave mode. 10 bit addressing: if M10 = `1', the interface is selected by the 10 bit address defined by IA9 to IA0. If M10 = `0' only the higher 7 bits IA7 to IA1 are used.
Note: If CSEL is changed during BB = `1' operation becomes unpredictable!
EMA ES ADR
RSC
M10
ICA9, ICA8 I2C Address Bits 9/8: this are the two MSBs of the device address in 10 bit mode. Possible Operation Modes EMA 0 0 1 1 ES1 0 1 0 1 Selected Operating Mode Interface disabled and initialized Slave mode Master mode Multimaster mode
Semiconductor Group
88
1996-06-01
SDA 30C263 / SDA 30C264
I2C Shifter Register Default after reset: undefined (MSB) Bit 7 Bit 6 Bit 5
ICSHI
SFR Address BAH
(LSB) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICSHI.7-.0 8-Bit transmit and receive shifter
Note: Write transfers to ICSHI are disabled by hardware during a transmission. Read operations are always possible.
I2C Address Register Default after reset: undefined (MSB) ICA7 ICA6 ICA5 ICA4 ICA3 ICA2 ICA1 (LSB) ICA0 ICADR SFR Address BBH
ICA7 ... ICA0 8-Bit address register: ICA7 ... ICA1 define the device address in 8 bit mode, in 10-bit mode all bits are used. I2C Baud Register 0 Default after reset: 00XX XXXXB (MSB) EDA0 ECL0 BD05 BD04 BD03 BD02 BD01 (LSB) BD00 ICBD0 SFR Address BCH
Semiconductor Group
89
1996-06-01
SDA 30C263 / SDA 30C264
I2C Baud Register 1 Default after reset: 00XX XXXXB (MSB) EDA1 EDA[1/0] ECL[1/0] BD[1/0]5 ... 0 ECL1 BD15
ICBD1
SFR Address BDH
(LSB) BD14 BD13 BD12 BD11 BD10
Enable Data Pin: EDAx = `1' enables data output for I2C operation. Enable Clock Pin: ECLx = `1' enables clock output for I2C operation. Baud Rate: the Baud Rate is 1/(4 x n) internal clock cycles. n is the binary number in ICBDi5 ... ICBDi0 plus 1, so n is in the range 1 ... 64. For example: 100 kBaud, 6 MHz internal clock -> n = 15 -> ICBD0 = CEH.
Possible Port Configurations EDA1 1 1 0 1 1 ECL1 1 1 X 0 1 EDA0 0 1 1 1 1 ECL0 X 0 1 1 1 P0.3 SCL1 SCL1/0 PORT PORT SCL1 P0.2 SDA1 SDA1 PORT SDA1 SDA1 P0.1 PORT SDA0 SDA0 SDA0 SDA0 P0.0 PORT PORT SCL0 SCL1/0 SCL0
Note 1: Any other combination results in PORT mode for P0.3 ... P0.0! Note 2: It is always possible to read the status of SDAx/SCLx by usual I/O-commands.
Semiconductor Group
90
1996-06-01
SDA 30C263 / SDA 30C264
2.11.2
Operation Description
After reset the port configuration must be defined. If the baud rates for both channels never change, they can be defined after reset once. Otherwise, they can be changed at any time.The desired operation mode can be selected at any time. In slave mode the device address has to be defined, 7 bit or 10 bit addressing can be selected. The interrupt enable bit EIC in IE may be set. ES has to be set to `1' to allow slave operation of the interface, CSEL is set to the desired channel. If the device is selected by another master, SLA changes from `0' to `1', an interrupt is generated and the CPU has to start the desired data transmission. If the device is receiver, TRX must be reset to `0'. Resetting IIN to `0' starts the reception phase. At the same time, SCL is released to allow the data transfer. If the device is transmitter, the CPU first writes the data to ICSHI and then sets TRX to `1', selects the state of ACK and reset IIN to `0'. This can be done with one byte write operation to ICCON. The device remains in slave mode until a stop condition is detected. This will also reset SLA to `0'. If master mode is required, the interface must have EMA set to `1'. Before any transmission, the CPU has to select the desired channel by setting or clearing CSEL. If the channel remains the same, no action is required. To become master on the bus is simple, if the device is the only possible master in the system. Generation of start and stop conditions is done by setting or clearing BUM. Transfer operations are controlled in the same manner like in slave mode. After setting BUM, the data contained in ICSHI is shifted out automatically after the start condition. A repeated start condition can be generated by setting RSC to `1'. RSC is reset to `0' automatically at the end of the repeated start condition. The CPU must write the slave address to ICSHI before setting RSC. The interface will automatically send the slave address after the repeated start condition. A stop condition is generated when BUM is reset to `0'. In Multimaster mode all the operations described above remain the same. The only exception is, that the bit AL in ICCON has to be checked by the CPU. If the interface lost the arbitration, AL is set to `1' and the interface switches to slave mode. If BB is set to `1' by a start condition on the bus and the CPU tries to set BUM, the request is suppressed and AL is set to `1'. AL can only be cleared by software.
Semiconductor Group
91
1996-06-01
SDA 30C263 / SDA 30C264
T0 Internal Clock, n = 5: Start Condition: SDA
T1
T2
T3
SCL Data/Acknowledge Bit: SDA
SCL Repeated Start: SDA
SCL Stop Condition: SDA
SCL
The high level of the signal is verified. If it is low, Ti is repeated. T0 ... T3 each Ti has a length of 1 ... 64 internal clocks as defined in ICBD0 and ICBD1.
UED08582
Figure 29 I2C Bus Events
Semiconductor Group
92
1996-06-01
SDA 30C263 / SDA 30C264
2.12
Advanced Function Register
This register contains some control bits, which enable and disable special functions or enhancements to previous controller generations. Therefore it is strongly recommended to use and to program only the described values! The on-chip clock generator of the SDA 30C263 contains the same clock divider, found in every 8051 compatible design. The clock divider divides the external clock frequency (oscillator frequency) by 2. To enhance clock performance by either doubling the internal clock frequency or by keeping the internal frequency constant and halving the external quartz frequency, the divider can be switched on or off by software. Advanced Function Register Default after reset: 0000 0XX1B (MSB) CDC CDC 0 0 0 0 0 0 (LSB) DJMP AFR SFR Address A6H
Clock divider control bit. If set, the clock divider is on. The internal clock frequency is half the external oscillator frequency. If cleared, the clock divider is off. The internal clock frequency is equal to the external oscillator frequency. After reset CDC is `1'. Reserved, always to be written with `0'. Disable Jump Mode: This bit controls the behaviour of the banking logic for the opcode JMP@A + DPTR. If this bit is set to `1', no banking operation is performed. If this bit is set to `0', JMP@A + DPTR switches in the same way as LJMP to the desired bank. After reset DJMP is `1'.
AFR.6 -.1 DJMP
Semiconductor Group
93
1996-06-01
SDA 30C263 / SDA 30C264
2.13
Instruction Set
The assembly language uses the same instruction set and the same instruction opcodes as the 8051 microcomputer family. 2.13.1 Rn direct @Ri #data #data 16 bit Notes on Data Addressing Modes - - - - - - Working register R0 ... R7. 128 internal RAM-locations, any I/O-port, control or status register. Indirect internal RAM-location addressed by register R0 or R1. 8-bit constant included in instruction. 16-bit constant included as bytes 2 & 3 of instruction. 128 software flags, any I/O-pin, control or status bit in special function registers.
Operations working on external data memory (MOVX ...) are used to access the additional 1024/2048 bytes of the extended internal data RAM (XRAM). 2.13.2 addr 16 addr 11 rel Notes on Program Addressing Modes - - - Destination address for LCALL & LJMP may be anywhere within the program memory address space. Destination address for ACALL & AJMP will be within the same 2 Kbyte of the following instruction. SJMP and all conditional jumps include an 8-bit offset byte. Range is + 127/ - 128 bytes relative to first byte of the following instruction.
Semiconductor Group
94
1996-06-01
SDA 30C263 / SDA 30C264
2.13.3
Instruction Set Description
Arithmetic Operations Mnemonic ADD ADD ADD ADD ADDC ADDC ADDC ADDC SUBB SUBB SUBB SUBB INC INC INC INC DEC DEC DEC DEC INC MUL DIV DA A, Rn A, direct A, @Ri A, #data A, Rn A, direct A, @Ri A, #data A, Rn A, direct A, @Ri A, #data A Rn direct @Ri A Rn direct @Ri DPTR AB AB A Description Add register to Accumulator Add direct byte to Accumulator Add indirect RAM to Accumulator Add immediate data to Accumulator Add register to Accumulator with Carry flag Add direct byte to A with Carry flag Add indirect RAM to A with Carry flag Add immediate data to A with Carry flag Subtract register from A with Borrow Subtract direct byte from A with Borrow Subtract indirect RAM from A with Borrow Increment Accumulator Increment register Increment direct byte Increment indirect RAM Decrement Accumulator Decrement register Decrement direct byte Decrement indirect RAM Increment Data Pointer Multiply A & B Divide A & B Decimal Adjust Accumulator Byte 1 2 1 2 1 2 1 2 1 2 1 1 1 2 1 1 1 2 1 1 1 1 1 Cycle 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 4 1
Subtract immediate data from A with Borrow 2
Semiconductor Group
95
1996-06-01
SDA 30C263 / SDA 30C264
Logical Operations Mnemonic ANL ANL ANL ANL ANL ANL ORL ORL ORL ORL ORL ORL XRL XRL XRL XRL XRL XRL CLR CPL RL RLC RR RRC A, Rn A, direct A, @Ri A, #data direct, A A, Rn A, direct A, @Ri A, #data direct, A A, Rn A, direct A, @Ri A, #data direct, A A A A A A A Description AND register to Accumulator AND direct byte to Accumulator AND indirect RAM to Accumulator AND immediate data to Accumulator AND Accumulator to direct byte OR register to Accumulator OR direct byte to Accumulator OR indirect RAM to Accumulator OR immediate data to Accumulator OR Accumulator to direct byte Exclusive-OR register to Accumulator Exclusive-OR direct byte to Accumulator Exclusive-OR indirect RAM to Accumulator Exclusive-OR immediate data to Accumulator Exclusive-OR Accumulator to direct byte Clear Accumulator Complement Accumulator Rotate Accumulator left Rotate A left through the Carry flag Rotate Accumulator right Rotate A right through Carry flag Swap nibbles within the Accumulator Byte 1 2 1 2 2 3 1 2 1 2 2 3 1 2 1 2 2 3 1 1 1 1 1 1 1 Cycle 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 2 1 1 1 1 1 1 1
direct, #data AND immediate data to direct byte
direct, #data OR immediate data to direct byte
direct, #data Exclusive-OR immediate data to direct
SWAP A
Semiconductor Group
96
1996-06-01
SDA 30C263 / SDA 30C264
Data Transfer Operations Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV A, Rn A, direct A, @Ri A, #data Rn, A Rn, direct Rn, #data direct, A direct, Rn direct, direct direct, @Ri direct, #data @Ri, A @Ri, direct @Ri, #data Description Move register to Accumulator Move direct byte to Accumulator Move indirect RAM to Accumulator Move immediate data to Accumulator Move Accumulator to register Move direct byte to register Move immediate data to register Move Accumulator to direct byte Move register to direct byte Move direct byte to direct Move indirect RAM to direct byte Move immediate data to direct byte Move Accumulator to indirect RAM Move direct byte to indirect RAM Move immediate data to indirect RAM Byte Cycle 1 2 1 2 1 2 2 2 2 3 2 3 1 2 2 3 1 1 1 1 1 1 2 1 1 2 2 2 2 1 2 1 2 2 2 2 2 2 2 2 2 1 1 1 1
DPTR, #data 16 Load Data Pointer with a 16-bit constant Move Code byte relative to PC to Accumulator
MOVC A@A + DPTR MOVC A@A + PC MOVX A, @Ri MOVX A, @DPTR MOVX @Ri, A MOVX @DPTR, A PUSH direct POP XCH XCH XCH direct A, Rn A, direct A, @Ri
Move Code byte relative to DPTR to Accumulator 1 Move External RAM (8-bit addr) to Accumulator 1 Move External RAM (16-bit addr) to Accumulator 1 Move A to External RAM (8-bit addr) Move A to External RAM (16-bit addr) Push direct byte onto stack Pop direct byte from stack Exchange register with Accumulator Exchange direct byte with Accumulator Exchange indirect RAM with Accumulator Exchange low-order digital indirect RAM with A 1 1 2 2 1 2 1 1
XCHD A, @Ri
Semiconductor Group
97
1996-06-01
SDA 30C263 / SDA 30C264
Boolean Variable Manipulation Mnemonic CLR CLR SETB SETB CPL CPL ANL ANL ORL ORL MOV MOV C bit C bit C bit C, bit C, /bit C, bit C, /bit C, bit bit, C Description Clear Carry flag Clear direct bit Set Carry flag Set direct bit Complement Carry flag Complement direct bit AND direct bit to Carry flag AND complement of direct bit to Carry OR direct bit to Carry flag OR complement of direct bit to Carry Move direct bit to Carry flag Move Carry flag to direct bit Byte 1 2 1 2 1 2 2 2 2 2 2 2 Cycle 1 1 1 1 1 1 2 2 2 2 1 2
Semiconductor Group
98
1996-06-01
SDA 30C263 / SDA 30C264
Program and Machine Control Operations Mnemonic ACALL addr 11 LCALL addr 16 RET RETI AJMP addr 11 LJMP JMP JZ JNZ JC JNC JB JNB JBC addr 16 @A + DPTR rel rel rel rel bit, rel bit, rel bit, rel SJMP rel Description Absolute subroutine call Long subroutine call Return from subroutine Return from interrupt Absolute jump Long jump Short jump (relative addr) Jump indirect relative to the DPTR Jump if Accumulator is zero Jump if Accumulator is not zero Jump if Carry flag is set Jump if Carry flag is not set Jump if direct bit set Jump if direct bit not set Jump if direct bit is set and clear bit Compare direct to A and jump if not equal Compare immediate to A and jump if not equal Compare immediate to register and jump if not equal Byte 2 3 1 1 2 3 2 1 2 2 2 2 3 3 3 3 3 3 3 2 3 1 Cycle 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1
CJNE A, direct rel CJNE A, #data, rel CJNE Rn, #data, rel
CJNE @Ri, #data, rel Compare immediate to indirect and jump if not equal DJNZ DJNZ NOP Rn, rel direct, rel Decrement register and jump if not zero Decrement direct and jump if not zero No operation
Semiconductor Group
99
1996-06-01
SDA 30C263 / SDA 30C264
2.13.4
Instruction Opcodes in Hexadecimal Order Mnemonic NOP AJMP LJMP RR INC INC INC INC INC INC INC INC INC INC INC INC JBC ACALL LCALL RRC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC DEC JB AJMP RET RL ADD ADD ADD ADD
100
Hex Code Number of Bytes 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 1 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 3 1 1 2 1 1 1 1 1 1 1 1 1 1 3 2 1 1 2 2 1 1
Operands code addr code addr A A data addr @R0 @R1 R0 R1 R2 R3 R4 R5 R6 R7 bit addr, code addr code addr code addr A A data addr @R0 @R1 R0 R1 R2 R3 R4 R5 R6 R7 bit addr, code addr code addr A A, #data A, data addr A, @R0 A, @R1
1996-06-01
Semiconductor Group
SDA 30C263 / SDA 30C264
2.13.4
Instruction Opcodes in Hexadecimal Order (cont'd) Mnemonic ADD ADD ADD ADD ADD ADD ADD ADD JNB ACALL RETI RLC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC ADDC JC AJMP ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL ORL
101
Hex Code Number of Bytes 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 1 1 1 1 1 1 1 1 3 2 1 1 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1
Operands A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 bit addr, code addr code addr A A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 code addr code addr data addr., A data addr, #data A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7
1996-06-01
Semiconductor Group
SDA 30C263 / SDA 30C264
2.13.4
Instruction Opcodes in Hexadecimal Order (cont'd) Mnemonic JNC ACALL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL ANL JZ AJMP XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL XRL JNZ ACALL ORL JMP MOV MOV MOV MOV
102
Hex Code Number of Bytes 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 2 1 2 3 2 2
Operands code addr code addr data addr, A data addr, #data A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 code addr code addr. data addr, A data addr, #data A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 code addr code addr C, bit addr @A + DPTR A, #data data addr, #data @R0, #data @R1, #data
1996-06-01
Semiconductor Group
SDA 30C263 / SDA 30C264
2.13.4
Instruction Opcodes in Hexadecimal Order (cont'd) Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV SJMP AJMP ANL MOVC DIV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV ACALL MOV MOVC SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB SUBB
103
Hex Code Number of Bytes 78 79 7A 7B 7C 7D 7E 7F 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F 2 2 2 2 2 2 2 2 2 2 2 1 1 3 2 2 2 2 2 2 2 2 2 2 3 2 2 1 2 2 1 1 1 1 1 1 1 1 1 1
Operands R0, #data R1, #data R2, #data R3, #data R4, #data R5, #data R6, #data R7, #data code addr code addr C, bit addr A, @A + PC AB data addr, data addr data addr, @R0 data addr, @R1 data addr, R0 data addr, R1 data addr, R2 data addr, R3 data addr, R4 data addr, R5 data addr, R6 data addr, R7 DPTR, #data 16 code addr bit addr, C A, @A + DPTR A, #data A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7
1996-06-01
Semiconductor Group
SDA 30C263 / SDA 30C264
2.13.4
Instruction Opcodes in Hexadecimal Order (cont'd) Mnemonic ORL AJMP MOV INC MUL reserved MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV ANL ACALL CPL CPL CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE CJNE PUSH AJMP CLR CLR SWAP XCH XCH XCH
104
Hex Code Number of Bytes A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 2 2 2 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 3 3 3 3 3 3 3 3 3 3 3 2 2 2 1 1 2 1 1
Operands C, /bit addr code addr C, bit addr DPTR AB @R0, data addr @R1, data addr R0, data addr R1, data addr R2, data addr R3, data addr R4, data addr R5, data addr R6, data addr R7, data addr C, /bit addr code addr bit addr C A, #data, code addr A, data addr, code addr @R0, #data, code addr @R1, #data, code addr R0, #data, code addr R1, #data, code addr R2, #data, code addr R3, #data, code addr R4, #data, code addr R5, #data, code addr R6, #data, code addr R7, #data, code addr data addr code addr bit addr C A A, data addr A, @R0 A, @R1
1996-06-01
Semiconductor Group
SDA 30C263 / SDA 30C264
2.13.4
Instruction Opcodes in Hexadecimal Order (cont'd) Mnemonic XCH XCH XCH XCH XCH XCH XCH XCH POP ACALL SETB SETB DA DJNZ XCHD XCHD DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ DJNZ MOVX AJMP MOVX MOVX CLR MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV
105
Hex Code Number of Bytes C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF 1 1 1 1 1 1 1 1 2 2 2 1 1 3 1 1 2 2 2 2 2 2 2 2 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1
Operands A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7 data addr code addr bit addr C A data addr, code addr A, @R0 A, @R1 R0, code addr R1, code addr R2, code addr R3, code addr R4, code addr R5, code addr R6, code addr R7, code addr A, @DPTR code addr A, @R0 A, @R1 A A, data addr A, @R0 A, @R1 A, R0 A, R1 A, R2 A, R3 A, R4 A, R5 A, R6 A, R7
1996-06-01
Semiconductor Group
SDA 30C263 / SDA 30C264
2.13.4
Instruction Opcodes in Hexadecimal Order (cont'd) Mnemonic MOVX ACALL MOVX MOVX CPL MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV Operands @DPTR, A code addr @R0, A @R1, A A data addr, A @R0, A @R1, A R0, A R1, A R2, A R3, A R4, A R5, A R6, A R7, A
Hex Code Number of Bytes F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF 1 2 1 1 1 2 1 1 1 1 1 1 1 1 1 1
Semiconductor Group
106
1996-06-01
SDA 30C263 / SDA 30C264
2.14
Differences between SDA 30C263 / SDA 30C264, SDA 30C163 / SDA 30C164 and SDA 5250 Package
1.
While SDA 30C16x devices are available in a P-LCC-68 package, SDA 30C26x devices are assembled in a P-MQFP-64-1 or P-MQFP-80-1 package. The SDA 30C26x devices in a P-MQFP-80-1 package are pinout compatible to the SDA 5250 TV Text parts. 2. Internal XRAM
1024 Byte for SDA 30C163 and SDA 30C263 2048 Byte for SDA 30C164 and SDA 30C264 1024 Byte for SDA 5250 3. I2C Bus
Available only for SDA 30C164 and SDA 30C264, not for SDA 30C163 and not for SDA 5250. 4. ADC Level Detection with Interrupt
Available only for SDA 30C164 and SDA 30C264, not for SDA 30C163 and not for SDA 5250. 5. PWM with 14 Bit Resolution
Available for SDA 30C164, SDA 30C263 and SDA 30C264 and SDA 5250, not available for SDA 30C163. 6. Output Signal PSEN
Only available for SDA 30C163 and SDA 30C164 in P-LCC-68 package (allows the connection of an external RAM device). 7. Port Lines P2.3 ... P2.7
Only available for SDA 30C163 and SDA 30C164 in P-LCC-68 package.
Semiconductor Group
107
1996-06-01
SDA 30C263 / SDA 30C264
8. 8.1 Access: AFR.0 AFR.1 AFR.2 AFR.3 AFR.4 AFR.5 AFR.6 AFR.7 8.2 Access: AFR.0 AFR.1 AFR.2 AFR.3 AFR.4 AFR.5 AFR.6 AFR.7
Advanced Function Register SDA 30C163 write-only, no read-modify-write operations allowed to be set to `1' to be set to `1' to be set to `1' to be set to `1' to be set to `1' to be set to `1' to be set to `1' CDC clock divider control bit; default: `1' (clock divider active) SDA 30C164 write-only, no read-modify-write operations allowed DJMP - disable jump mode (special feature of the memory management unit); default: `1' to be set to `0' to be set to `0' ERW - enable RD/WR-signals at port 3 lines for external data memory; default: `0' to be set to `0' to be set to `0' to be set to `0' CDC - clock divider control bit; default: `0' (clock divider off)
Semiconductor Group
108
1996-06-01
SDA 30C263 / SDA 30C264
8.3 Access: AFR.0 AFR.1 AFR.2 AFR.3 AFR.4 AFR.5 AFR.6 AFR.7 8.4 Access: AFR.0 AFR.1 AFR.2 AFR.3 AFR.4 AFR.5 AFR.6 AFR.7 9.
SDA 30C26x write-only, no read-modify-write operations allowed DJMP - disable jump mode (special feature of the memory management unit); default: `1' to be set to `0' to be set to `0' to be set to `0' to be set to `0' to be set to `0' to be set to `0' CDC clock divider control bit; default: `1' (clock divider active) SDA 5250 write-only, no read-modify-write operations allowed to be set to `0' to be set to `0' to be set to `0' to be set to `0' to be set to `1' to be set to `1' WDT used for watchdog timer CDC clock divider control bit; default: `0' (clock divider OFF) Infrared Timer
Only available for SDA 5250. 10. Reset Input
Strong pulldown for SDA 30C164, weak pullup for SDA 30C163, SDA 30C26X and SDA 5250.
Semiconductor Group
109
1996-06-01
SDA 30C263 / SDA 30C264
3 3.1
Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. to 7 1 0 - 65 70 125 V W C C - 0.5 Unit
Parameter
Voltage on any pin with respect to ground (VSS) VS Power dissipation Ambient temperature under bias Storage temperature
Ptot TA Tstg
Note: Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
3.2 DC Characteristics Symbol min. L-input voltage H-input voltage (all except XTAL1) H-input voltage (XTAL1) L-output voltage L-output voltage (P03 ... P00 only) H-output voltage (ports 1, 3, 4) H-output voltage (A0 ... A16, PWM/UART mode, ALE) Logical `0' input current (D0 ... D7, ports 1,3,4) Input leakage current (port 0, P20 ... P23)
Semiconductor Group
TA = 0 to 70 C; VDD = 5 V 10 %, VSS = 0 V
Parameter Limit Values typ. max. 0.8 V V V V V V V - 0.5 2.0 0.7 VDD - - 2.4 2.4 Unit Test Condition
VIL VIH VIH1 VOL VOL1 VOH VOH1
VDD +
0.5
VDD +
0.5 0.45 0.6 - -
IOL = 3.2 mA IOL = 5.0 mA IOH = - 40 A IOH = - 1.6 mA
IIL
- 50
- 200
A
VIN = 0.45 V
0.45 V VIN VDD
ILI
10
A
110
1996-06-01
SDA 30C263 / SDA 30C264
3.2
DC Characteristics (cont'd) Symbol min. Limit Values typ. max. t.b.d. 1 t.b.d. t.b.d. 10 45 50 0.5 1 0.5 x A V mA A pF pF A LSB V V V V A - 0 Unit Test Condition
TA = 0 to 70 C; VDD = 5 V 10 %, VSS = 0 V
Parameter Logical `0' input current (RST) Reset voltage (RST) Power supply current Power-down current Pin capacitance Analog input capacitance ADC input current error Analog ground voltage Analog reference voltage Analog supply difference voltage Analog input voltage
IRST VRST IDD IPD CIO CI
VDD = 5 V; fINT = 12 MHz VDD = 5 V fC = 1 MHz
IANA ADC total unadjusted TUE VSSA VDDA VADELTA VAI IDDA VSS
0.5 x
VDD VDD VDD VDDA +
0.2 50
VDD
0.5 x
VDD VAGND -
0.2
VDDA supply current
VDDA = 5 V
Semiconductor Group
111
1996-06-01
SDA 30C263 / SDA 30C264
3.3
AC Characteristics
Program Memory and External Clock Drive Characteristics
TA = 0 to 70 C; VDD = 5 V 10 %, VSS = 0 V
Parameter Symbol Limit Values Variable Clock 1/tCLCL = 1.0 MHz to 12 MHz min. Cycle time Address out to valid instr in Oscillator period External clock high time External clock low time External clock rise time External clock fall time max. - 2.3 x tCLCL 1000 ns ns ns ns ns 15 15 ns ns Unit
tCY tAVIV tCLCL tCHCX tCLCX tCLCH tCHCL
6 tCLCL - 83.3 25 25
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at TA = 25 C and the given supply voltage.
Semiconductor Group
112
1996-06-01
SDA 30C263 / SDA 30C264
AC Testing Input, Output, Float Waveforms AC testing inputs are driven at VDD - 0.5 V for a logic `1' and at 0.45 V for a logic `0'. Timing measurements are made at VIHmin for a logic `1' and at VIHmax for a logic `0'. For timing purposes a port pin is no longer floating, when a 100 mV change from load voltage occurs.
VDD - 0.5 V
0.45 V
0.2 VDD + 0.9 Test Points 0.2 VDD - 0.1
VLOAD + 0.1 V VLOAD VLOAD 0.1 V Timing Reference Points
VOH - 0.1 V VOL + 0.1 V
UED04592
Figure 30 I/O-Waveform for AC Tests
Semiconductor Group
113
1996-06-01
SDA 30C263 / SDA 30C264
4
Applications
+5 V
C
XTAL1 33 pF 1 ... 12 MHz
VDD
VSS
P0.0 ... 7 P1.0 ... 7 P2.0 ... 3
8 8 4
Port 0 Port 1 ADC
C
XTAL2 33 pF RST P3.0 P3.1 P3.2/INT0 P3.3/INT1 Port 3 P3.4/T0 P3.5/T1 P3.6/RxD P3.7/TxD
SDA 30C263 SDA 30C264
A16 P4.0/A17 P4.1/A18 A0 ... 15 D0 ... 7 ALE 2 16 8
Memory Extension Port 4 Address Data Interface
VSSA VDDA
UES08583
Figure 31 Application Circuit
Semiconductor Group 114 1996-06-01
SDA 30C263 / SDA 30C264
Waveforms
t CY t ALAH
ALE
t ALIV
t PXIX
Inst IN
t PXAV
D
Inst IN
Inst IN
t AVIV
A A0-16 A0-16
UED04734
Figure 32 Program Memory Read Cycle
t CHCX VDD-0.5
0.7 VDD 0.2 VDD-0.1
t CLCH
t CHCL
t CLCX t CLCL
UED04735
Figure 33 External Clock Cycle
Semiconductor Group 115 1996-06-01
SDA 30C263 / SDA 30C264
5
Package Outlines P-MQFP-64-1 (Plastic Metric Quad Flat Package)
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 116
Dimensions in mm
1996-06-01
GPM05250
SDA 30C263 / SDA 30C264
P-MQFP-80-1 (Plastic Metric Quad Flat Package)
0.25 min 2 +0.1 -0.05 2.45 max
0.65 0.3 0.08 12.35 17.2 14
1)
0.88
C
0.1 0.12 M A-B D C 80x 0.2 A-B D 80x 0.2 A-B D H 4x
D A B
14 1) 17.2
80 1 Index Marking
0.6x45
1) Does not include plastic or metal protrusions of 0.25 max per side
GPM05249
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". SMD = Surface Mounted Device Semiconductor Group 117
Dimensions in mm
1996-06-01
7max
H
0.15 +0.08 -0.02
SDA 30C263 / SDA 30C264
6
Index
A Absolute Maximum Ratings 110 AC Characteristics 112 ACC, A 35 ADC Control Register 82 ADC Level Detection with Interrupt 107 ADC Start Register 82 ADC-Data Register 83 ADCON 36, 82 ADDAT 36, 83 Addressing Modes 22, 94 Advanced Function Register 93, 108 AFR 35, 93 Analog Detector 83 Analog Digital Converter 36, 81 Analog-to-Digital Converter 8 Applications 114 Architecture 7, 18 Arithmetic Operations 95 Arithmetic Registers 35 B B 35 Banking 25 Baud Rates 65 Boolean Variable Manipulation B-Register 35 C CPU Hardware 19 CPU Timing 21 D DAPR 36, 82 Data Pointer 21 Data Transfer Operations 97 DC Characteristics 110 DECON 36, 83 DELOW 36, 84 DESEL 36, 84 Detector-Control Register 83 Detector-Lower Register 93 Detector-Select Register 84
Semiconductor Group
Detector-Upper Register DEUP 36, 84 Differences 107 DPH 35 DPL 35 DPSEL 35 DPTR 21
84
E Electrical Characteristics 110 External Interrupts 44 External Program Memory 24 External Program Memory Interface F Features 7 Functional Block Diagram
7
17
G General Purpose Timers/Counters 52 Generated Commonly Used Baud Rates 66 I I/O-Lines 8 I/O-Port Registers 35 I2C Bus 107 I2C Registers 37 I2C Serial Interface 86 I2C-Address Register 89 I2C-Baud Register 0 89 I2C-Baud Register 1 90 I2C-Control Register 87 I2C-Mode Register 88 I2C-Shifter Register 89 ICADR 37, 89 ICBD0 37, 89 ICBD1 37, 90 ICCON 37, 87 ICMOD 37, 88 ICSHI 37, 89 IE 35, 41 Infrared Timer 109 Instruction Opcodes in Hexadecimal Order 100
118 1996-06-01
98
SDA 30C263 / SDA 30C264
Instruction Set 94 Internal Data Memory Address Space 32 Internal Data RAM 19, 30 Internal RAM-Bit Addresses 33 Internal XRAM 107 Interrupt Control 39 Interrupt Control Registers 35 Interrupt Enable Register IE 41 Interrupt Nesting 43 Interrupt Priority Register 42 Interrupt Request Control Register 45 Interrupt Sources 38 Interrupt System 38, 40 Introduction 5 IP0 35, 42 IP1 35, 42 IRCON 35, 45 L Logical Operations 96
M Memory Extension 24 Memory Extension Bank 27 Memory Extension Mode 27 Memory Organization 24 MEX1 27, 35 MEX2 27, 35 Multiprocessor Communication O On-Chip RAM 7 Output Signal PSEN
64
107
P P0 35 P1 35 P2 35 P3 35 P4 35 Package 107 Package Outlines 116 PAGE 0 35 PAGE 1 35 Page Registers 31
Semiconductor Group
PCON 35, 49 Pin Configuration 9, 10 Pin Definitions and Functions 11 P-MQFP-64-1 116 P-MQFP-80-1 117 Port Lines P2.3 - P2.7 107 Ports and I/O-Pins 50 Power Control Register 49 Power-Down Operations 49 Priority within Level 43 Processor Reset 48 Program and Machine Control Operations 100 Program and Machine Control Operations 99 Program Status Word 20 PSW 20, 35 Pulse Width Modulation Unit 8, 78 Pulse Width Modulator Registers 37 PWCH 37, 81 PWCL 37, 80 PWCOMP0 37 PWCOMP0 ... 5 79 PWCOMP1 37 PWCOMP2 37 PWCOMP3 37 PWCOMP4 37 PWCOMP5 37 PWCOMP6 37 PWCOMP6, 7 79 PWCOMP7 37 PWEXT 6, 7 80 PWEXT6 37 PWEXT7 37 PWM Compare Registers 79 PWM Extension Registers 80 PWM High Counter Registers 81 PWM Low Counter Registers 80 PWM with 14 Bit Resolution 107 PWME 37, 79 PWM-Enable Register 79
119
1996-06-01
SDA 30C263 / SDA 30C264
R Read Modify-Write 51 Response Time 47 S SBUF 37 SCON 37, 63 Serial Interface 7, 62 Serial Interface Registers 37 Serial Port Control Register 63 Serial Port Mode 0 70 Serial Port Mode 1 72 Serial Port Mode 2 74 Serial Port Mode 3 76 Serial Port Mode Selection 64 SP 21, 35 Special Function Register Bit Address Space 34 Special Function Register Overview 35 Stack Pointer 21 System Control Registers 35 T TCON 36, 44, 56 TH0 36 TH1 36 Timer 0/1 Control Register 56 Timer 0/1 Registers 36 Timer and Interrupt Control Register Timers 8 TL0 36 TL1 36 TMOD 36 W Watchdog High Byte 61 Watchdog Low Byte 61 Watchdog Timer 59 Watchdog Timer Control Register Watchdog Timer Registers 36 Watchdog Timer Reload Register Waveforms 113 WDCON 36, 60 WDTH 36, 61
Semiconductor Group
WDTL 36, 61 WDTREL 36, 60
44
60 60
120
1996-06-01

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